GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

8. Debugging GTS Transceiver Links with Transceiver Toolkit

The GTS PMA/FEC Direct PHY Intel® FPGA IP supports the Transceiver Toolkit as part of debugging tools that you can use to debug your GTS Transceiver Links. The Transceiver Toolkit helps you to optimize high-speed serial links in your board design by providing real-time control, monitoring, and debugging of the GTS transceiver links running on your board.

The Transceiver Toolkit features allow you to:
  • Test and tune transceiver link signal quality through a combination of metrics.
  • Run a single bit-error-rate (BER) test on a single channel or multiple simultaneous BER tests on multiple channels.
  • Use Auto Sweep feature to sweep transceiver settings to determine the parameters that support best BER value.
  • Generate and check different PRBS patterns to provides you the ability to stress your link according to your system specifications.
  • View the receiver horizontal and vertical eye margin during testing.
The GTS Transceiver Toolkit runs from the System Console framework.