GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP

Use the GTS PMA/FEC Direct PHY Intel FPGA IP in the Quartus® Prime Pro Edition software to configure the PMA PHY for your protocol implementation. To instantiate the IP, follow these steps:

  1. To specify the target device family, click Assignments -> Device, and then select an Agilex™ 5 device.
  2. Click ToolsIP Catalog, type PMA in the search field, and select the GTS PMA/FEC Direct PHY Intel FPGA IP (under Interface Protocol). The IP parameter editor opens.
  3. In the parameter editor, specify the parameters to customize the GTS PMA/FEC Direct PHY Intel FPGA IP for your protocol implementation. Select one of the following PMA usage modes. The parameter editor guides your parameter value selections.
    • PMA Direct mode
    • FEC Direct mode
  4. When parameterization is complete, click the Generate button, and then click the Generate HDL button. Your IP variation RTL and supporting files generate according to your specifications, and are added to your Quartus® Prime project. The top-level file generated with the IP instance includes all the available ports for your configuration. Use these ports to connect the GTS PMA/FEC Direct PHY Intel FPGA IP to other IP cores in your design, such as the GTS System PLL Clocks Intel FPGA IP, GTS Reset Sequencer Intel FPGA IP, TX and RX serial data pins, and the data checker IP.

    The Agilex™ 5 E-Series and D-Series GTS PMA/FEC Direct PHY Intel FPGA IP supports only the following simulators:

    • VCS* MX
    • QuestaSim*
    • Xcelium*