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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. PCS Direct Signals: IEEE
3.4.6. PCS Direct Signals: IEEE_FLEXE_66/PCS66
3.4.7. Custom Cadence Control and Status Signals
3.4.8. RX PMA Status Signals
3.4.9. TX and RX PMA and Core Interface FIFO Signals
3.4.10. Avalon Memory-Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
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3.13.2.2. GTS Attribute Access Method Example 2
The following examples demonstrate the steps to perform polarity inversion for the GTS PMA.
To reverse the polarity of TX p and n pins:
- Assert TX reset.
- Write 0x1A065 to address 0xA403C.
- Poll address 0xA4040 until bit 14 = 0 and bit 15 = 1.
- Write 0x12065 to address 0xA403C.
- Poll address 0xA4040 until bit 14 = 0 and bit 15 = 0.
- Deassert TX reset.
To reverse the polarity of RX p and n pins:
- Assert RX reset.
- Write 0x1A066 to address 0xA403C.
- Poll address 0xA4040 until bit 14 = 0 and bit 15 = 1.
- Write 0x12066 to address 0xA403C.
- Poll address 0xA4040 until bit 14 = 0 and bit 15 = 0.
- Deassert RX reset.
To revert back the polarity of TX p and n pins:
- Assert TX reset.
- Write 0x0A065 to address 0xA403C.
- Poll address 0xA4040 until bit 14 = 0 and bit 15 = 1.
- Write 0x02065 to address 0xA403C.
- Poll address 0xA4040 until bit 14 = 0 and bit 15 = 0.
- Deassert TX reset.
To revert back the polarity of RX p and n pins:
- Assert RX reset.
- Write 0x0A066 to address 0xA403C.
- Poll address 0xA4040 until bit 14 = 0 and bit 15 = 1.
- Write 0x02066 to address 0xA403C.
- Poll address 0xA4040 until bit 14 = 0 and bit 15 = 0.
- Deassert RX reset.