GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.8.9. TX PLL Lock Loss

Figure 59. Reset Sequence for TX PLL Lock Loss
The figure above illustrates the sequence in the event of a TX PLL lock loss:
  1. o_tx_pll_locked deasserts, indicating PLL lost lock of the reference clock.
  2. o_tx_ready deasserts, indicating that the datapath no longer operational.
  3. Assert i_tx_reset.
  4. o_tx_reset_ack asserts, indicating that the datapaths are in reset. o_tx_reset_ack stay asserted until i_tx_reset deassert.
  5. You then deassert i_tx_reset to bring TX out of reset.
  6. o_tx_pll_locked asserts as the TX PLL locks to the reference clock.
  7. o_tx_ready asserts.
Note: Due to simulation model limitations, you cannot simulate this condition in simulation.