GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.4.6. PCS Direct Signals: IEEE_FLEXE_66/PCS66

Table 38.  PCS Direct Signals: IEEE_FLEXE_66/PCS66
Signal Name Clocks Domain/Resets Direction Description
i_tx_pcs66_d[65:0] tx_coreclkin Input

Drive this data bus with the 66-bit data blocks from the source. The two least significant bits are the header sync bits.

In FlexE mode, the TX PCS scrambles the 66-bit data block and stripes the data blocks across the transceiver channels.

i_tx_pcs66_valid tx_coreclkin Input Drive this signal high to qualify the 66-bit data block on the i_tx_pcs66_d input data bus.
i_tx_pcs66_am tx_coreclkin Input Drive valid 66-bit data blocks when this signal has been asserted. Do not drive valid data blocks when this signal is deasserted.
o_tx_pcs66_ready tx_coreclkin Output In the FlexE mode, assert this signal so that the TX PCS inserts alignment markers, ignoring the data on the i_tx_pcs66_d input.
o_rx_pcs66_d[65:0] rx_coreclkin Output Output data bus that receives Ethernet frames or MII control bytes, MII encoded. o_rx_mii_d[7:0] holds the first byte received.
o_rx_pcs66_valid rx_coreclkin Output PCS66 data valid signal. The signal indicates valid data on PCS66 ports.
o_rx_pcs66_am_valid rx_coreclkin Output Alignment marker indicator (applicable for RS-FEC). This signal indicates the blocks currently on o_rx_pcs66_d have been identified as alignment markers.