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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. PCS Direct Signals: IEEE
3.4.6. PCS Direct Signals: IEEE_FLEXE_66/PCS66
3.4.7. Custom Cadence Control and Status Signals
3.4.8. RX PMA Status Signals
3.4.9. TX and RX PMA and Core Interface FIFO Signals
3.4.10. Avalon Memory-Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
Visible to Intel only — GUID: mxx1708730579467
Ixiasoft
8.1. GTS Transceiver Toolkit Parameter Settings
The following table describes the transceiver toolkit parameter settings.
Parameter | Description | Control Pane |
---|---|---|
Bit error rate (BER) | Reports the number of errors divided by bits tested since the last reset of the checker. When RX CDR is locked to reference clock or PRBS checker is not locked, the BER reported is not reliable. | Receiver pane |
Clear Stats | Clear the current number of bits tested, number of error bits and BER. | Receiver pane |
Hard PRBS checker running | Not Running: checker stops. Running: checker is checking, and data pattern is locked. |
Receiver pane |
Hard PRBS generator running | Not Running: generator stops. Running: generator is sending a pattern. |
Transmitter pane |
Inject Error | Inject a bit error in the transmitter PRBS pattern. | Transmitter pane |
Loopback mode | Select the loopbacks mode. The available options are:
|
Receiver pane |
Number of bits tested | Specifies the number of bits tested since the last reset of the checker. When RX CDR is locked to reference clock or PRBS checker is not locked, the BER reported is not reliable | Receiver pane |
Number of error bits | Specifies the number of error bits encountered since the last reset of the checker. When RX CDR is locked to reference clock or PRBS checker is not locked, the BER reported is not reliable | Receiver pane |
PRBS pattern | Select the test pattern for the bit error test. | Transmitter and receiver pane |
RX PMA Settings | RX Equalization settings.
Note: You can control these settings only when you are using the manual adaptation mode.
|
Receiver pane |
RX PMA Advance Settings | Displays the values of the DFE Data Taps 2 through 16.
Note: These parameters are read only to view the values.
|
Receiver pane |
Eye Viewer | Provides interface for measuring the Eye Width and Eye Height as well as saving the measurements into CSV. | Receiver Pane |
Set Working Directory | Allows you to change the folder used as the working directory. You can use it you want to save the exported Eye measurements CSV into your chosen path | Toolkits Parameters tab |
Invert Polarity | Allows you to enable TX or RX polarity inversion | Transmitter and receiver pane |
RX CDR locked to data | Locked: Indicates the receiver CDR is in lock-to-data (LTD) mode. Not Locked: Indicates the receiver CDR is not locked to incoming data. |
Receiver pane |
RX CDR locked to ref clock | Locked: Indicates the receiver CDR is in lock-to-reference (LTR) mode. Not Locked: Indicates the receiver CDR is not locked to reference clock. Don't Care: When the receiver CDR is in LTD mode. |
Receiver pane |
RX Reset PMA | Reset the RX datapath. | Receiver pane |
Start | Starts the pattern generator or checker on the channel to verify incoming data. | Transmitter and receiver pane |
Stop | Stops generating patterns and testing the channel. | Transmitter and receiver pane |
TX Equalization Parameters | Post_tap_1 Main_tap Pre_tap_1 Pre_tap_2 |
Transmitter pane and receiver pane |
TX PLL Locked | Locked: Indicates TX PLL locks to reference clock. | Transmitter pane |
TX Reset PMA | Reset the TX PMA datapath. | Transmitter pane |