Visible to Intel only — GUID: uih1681938758915
Ixiasoft
Visible to Intel only — GUID: uih1681938758915
Ixiasoft
3.4. Signal and Port Reference
The following section describes all GTS PMA/FEC Direct PHY Intel FPGA IP ports and signals.
Each tx_parallel_data and rx_parallel_data bus is exposed as 80 bits per lane. Some bits map to special functionality.
Each PMA channel transmits and receives 80 bits, parallel data interface. The determination of active and inactive ports depends on specific configuration parameters, such as the number of lanes and the PMA width.
For details about mapping of data and control signals, refer to Parallel Data Mapping Information.
When you enable the Provide separate interface for each PMA option for the GTS PMA/FEC Direct PHY Intel FPGA IP, the PHY presents separate data and clock interfaces for each PMA lane, rather than a wide bus. Each PMA lane signal name is appended with a _xcvr<n> suffix, with n = PMA index number. When Provide separate interface for each PMA is disabled, the signal name does not append _xcvr<n>.
For example, if you enable Provide separate interface for each PMA for two PMA lane configuration, the serial port signal names appear as:
o_tx_serial_data_xcvr0, o_tx_serial_data_xcvr1.
If you disable Provide separate interface for each PMA for two lane PMA configuration, the serial port signal name appears as: o_tx_serial_data[1:0].
The following are the signals that do not have separate interfaces when Provide separate interface for each PMA option is on:
- i_system_pll_clk
- i_tx_reset, i_rx_reset, o_tx_reset_ack, o_rx_reset_ack, o_tx_ready, o_rx_ready
- rsfec signals
- i_tx_cadence_fast_clk, i_tx_cadence_slow_clk, i_tx_cadence_slow_clk_locked
Variable | Values | Description |
---|---|---|
<N> | 1, 2, 4, 6, 8 |
N is the number of PMA lanes. |
<n> | 0 to N-1 | n is the PMA index number. |
<X> | X=1 |
X is 1 always. |
<M> | 0 to M-1 | M is the number of banks per side of the device. |
<K p > | Ceiling(log2(N)) K p = 0, 1, 2, 3, 4 for N = 1, 2, 4 |
K p is the PMA reconfiguration interface address. K p =0 if separate Avalon® interface per PMA is enabled K p =Ceiling(log2(N) if separate Avalon® interface per PMA is disabled. |
Section Content
TX and RX Parallel and Serial Interface Signals
TX and RX Reference Clock and Clock Output Interface Signals
Reset Signals
FEC Signals
PCS Direct Signals: IEEE
PCS Direct Signals: IEEE_FLEXE_66/PCS66
Custom Cadence Control and Status Signals
RX PMA Status Signals
TX and RX PMA and Core Interface FIFO Signals
Avalon Memory-Mapped Interface Signals