GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

2.6. Clock Architecture

The Agilex™ 5 FPGA GTS transceivers have two types of clock networks:
  • Reference clock network
  • Datapath clock network
The following figure is a simplified block diagram of the clock networks.
Figure 21. Clock Network
Both the system PLL and the PMA clock get their reference clock from the reference clock network. The datapath clock network is accessible by all enabled digital blocks and is driven by a clock from either the PMA or the system PLL. PMA clocking includes the use of a Transmit PLL (TX PLL) or Clock Data Recovery (CDR) for the transmit and receive clocks, respectively.