Visible to Intel only — GUID: cjw1681416886625
Ixiasoft
Visible to Intel only — GUID: cjw1681416886625
Ixiasoft
3.1.1. PMA Direct Supported Modes
The GTS PMA/FEC Direct PHY Intel FPGA IP currently supports the following PMA Direct modes:
- NRZ modulation
- Duplex, TX simplex and RX simplex modes for both PMA clocking and system PLL clocking with 8, 10, 16, 20, and 32 data widths.
- Supports x2, x4, x6 and x8 bonding on the TX path
- Supports configurable FIFO modes: PMA interface FIFO (elastic and register modes) and core interface mode (phase compensation)
Clocking Mode | Double Width/Single Width Mode 24 | PMA Interface Width | PMA Interface FIFO (TX/RX) | Core Interface FIFO (TX/RX) |
---|---|---|---|---|
System Clocking | DW | 8, 10, 16 ,20,32 | Elastic/Elastic |
Phase Compensation/Phase Compensation |
SW | 8, 10 ,16, 20, 32 | Elastic/Elastic |
Phase Compensation/Phase Compensation |
|
PMA Clocking |
DW | 8, 10, 16, 20, 32 | Register/Register |
Phase Compensation/Phase Compensation |
8, 10, 16, 20, 32 | Register/Register |
Elastic 25/Phase Compensation |
||
8, 10, 16, 20, 32 | Register/Register |
Phase Compensation/Elastic25 | ||
8, 10, 16, 20, 32 | Register/Register |
|||
SW | 8, 10, 16, 20, 32 | Register/Register |
Phase Compensation/Phase Compensation |
|
8, 10, 16, 20, 32 | Register/Register |
Elastic25/Phase Compensation |
||
8, 10, 16, 20,32 | Register/Register |
Phase Compensation/Elastic25 |
||
8, 10, 16, 20, 32 | Register/Register |
For multiple lanes and TX deskew function, core interface FIFO must be set to phase compensation mode.