GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.1.1. PMA Direct Supported Modes

The GTS PMA/FEC Direct PHY Intel FPGA IP currently supports the following PMA Direct modes:

  • NRZ modulation
  • Duplex, TX simplex and RX simplex modes for both PMA clocking and system PLL clocking with 8, 10, 16, 20, and 32 data widths.
  • Supports x2, x4, x6 and x8 bonding on the TX path
  • Supports configurable FIFO modes: PMA interface FIFO (elastic and register modes) and core interface mode (phase compensation)
Table 17.  PMA Direct Mode Support
Clocking Mode Double Width/Single Width Mode 24 PMA Interface Width PMA Interface FIFO (TX/RX) Core Interface FIFO (TX/RX)
System Clocking DW 8, 10, 16 ,20,32

Elastic/Elastic

Phase Compensation/Phase Compensation

SW 8, 10 ,16, 20, 32

Elastic/Elastic

Phase Compensation/Phase Compensation

PMA Clocking

DW 8, 10, 16, 20, 32

Register/Register

Phase Compensation/Phase Compensation

8, 10, 16, 20, 32

Register/Register

Elastic 25/Phase Compensation

8, 10, 16, 20, 32

Register/Register

Phase Compensation/Elastic25
8, 10, 16, 20, 32

Register/Register

Elastic25/Elastic25

SW 8, 10, 16, 20, 32

Register/Register

Phase Compensation/Phase Compensation

8, 10, 16, 20, 32

Register/Register

Elastic25/Phase Compensation

8, 10, 16, 20,32

Register/Register

Phase Compensation/Elastic25

8, 10, 16, 20, 32

Register/Register

Elastic25/Elastic25

For multiple lanes and TX deskew function, core interface FIFO must be set to phase compensation mode.

24 The Double width (DW) mode is when the Enable TX/RX double width transfer parameter in the GTS PMA/FEC Direct PHY Intel FPGA IP GUI is enabled. When it is enabled, you can clock the FPGA core logic with a half rate clock. Single width (SW) mode is when this parameter is not enabled.
25 The current release of the Quartus® Prime Pro Edition software does not support Elastic mode.