GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

5.3. IP Port List

Table 74.  GTS Reset Sequencer Intel FPGA IP Port List

N is number of channels used.

M is number of banks per side of the device.

Signal Name Direction Width Description
i_src_rs_req Input N Request from SRC to GTS Reset Sequencer Intel FPGA IP for reset operation. Asserts when there is a request to toggle reset.
o_src_rs_grant Output N Grant from GTS Reset Sequencer Intel FPGA IP to SRC. Asserts when the reset request is granted by the Reset Sequencer.
i_src_rs_priority Input N
Binary priority input
  • 0 - Low priority
  • 1 - High priority

This port used to set priority for a channel that you need to prioritize the reset sequence when there are multiple channels being reset simultaneously. You must tie the input to 0 except for the priority channel which needs to be set to 1.

o_pma_cu_clk Output M
PMA control unit clock output, one per bank for each side of the device. This clock port must be connected to the GTS PMA/FEC Direct PHY Intel FPGA IP and all other protocol IPs.
Note: o_pma_cu_clk signal is only for use by the PMA control unit and you must not use it elsewhere.