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Ixiasoft
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Ixiasoft
2.1. Building Blocks
The number of GTS transceiver banks varies depending on device density and package variants. Refer to Agilex™ 5 FPGAs and SoCs Family Plan for details on the GTS transceiver count.
Refer to the following figures for the respective GTS transceiver bank layout. In devices with options for smaller packages, some GTS transceiver banks are downbonded (GTS pins not bonded out at package) and not available for use, except for the system PLL that remains available for use to clock the FPGA core logic.
Configuration | PCIe* Hard IP | MAC | PCS | FEC | PMA | Example Protocols |
---|---|---|---|---|---|---|
Hardened PCIe* IP | Yes | No | No | No | Yes | PCIe* |
Hardened Ethernet IP | No | Yes | Yes | Optional | Yes | 10G/25G Ethernet |
Hardened USB 3.1 IP 3 | No | No | No | No | Yes | USB3.1 |
PCS Direct | No | No | Yes | Optional4 | Yes | CPRI (64B/66B), FlexE, OTN |
FEC Direct | No | No | No | Yes | Yes | Fibre Channel 16G |
PMA Direct | No | No | No | No | Yes | Basic, CPRI (8B/10B), HDMI, SDI, DisplayPort, JESD204B/C SATA, GPON 5, Fibre Channel, Interlaken |
Section Content
PMA
FEC
PCS
Ethernet MAC
PCI Express Hard IP
PLL and Clock Networks
Avalon Memory-Mapped Interface