GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

2.1. Building Blocks

A GTS transceiver bank consists of four PMA channels, hardened IPs (FEC, PCS, PCIe, and Ethernet MAC), a system PLL, and clock networks (for reference clock and datapath clock).
Figure 1. High-Level Block Diagram of a GTS Transceiver Bank

The number of GTS transceiver banks varies depending on device density and package variants. Refer to Agilex™ 5 FPGAs and SoCs Family Plan for details on the GTS transceiver count.

Refer to the following figures for the respective GTS transceiver bank layout. In devices with options for smaller packages, some GTS transceiver banks are downbonded (GTS pins not bonded out at package) and not available for use, except for the system PLL that remains available for use to clock the FPGA core logic.

Figure 2. GTS Transceiver Bank Layout for E-Series FPGAs with 24 GTS TransceiversApplicable to Device Group A and Device Group B
Figure 3. GTS Transceiver Bank Layout for E-Series FPGAs with 16 GTS TransceiversApplicable to Device Group A and Device Group B
Figure 4. GTS Transceiver Bank Layout for E-Series FPGAs with 12 GTS TransceiversApplicable to Device Group A and Device Group B
Figure 5. GTS Transceiver Bank Layout for E-Series FPGAs with 4 GTS Transceivers
The following figures show the different packages and GTS transceiver combinations for the D-Series FPGAs.
Figure 6. GTS Transceiver Bank Layout for D-Series FPGAs with 32 GTS Transceivers
Figure 7. GTS Transceiver Bank Layout for D-Series FPGAs with 24 GTS Transceivers
Figure 8. GTS Transceiver Bank Layout for D-Series FPGAs with 16 GTS Transceivers
Figure 9. GTS Transceiver Bank Layout for D-Series FPGAs with 8 GTS Transceivers
The following table shows the hard IP configurations supported by the PMA for enabling various interface protocols.
Table 2.  Hard IP Configurations Supported with PMA
Configuration PCIe* Hard IP MAC PCS FEC PMA Example Protocols
Hardened PCIe* IP Yes No No No Yes PCIe*
Hardened Ethernet IP No Yes Yes Optional Yes 10G/25G Ethernet
Hardened USB 3.1 IP 3 No No No No Yes USB3.1
PCS Direct No No Yes Optional4 Yes CPRI (64B/66B), FlexE, OTN
FEC Direct No No No Yes Yes Fibre Channel 16G
PMA Direct No No No No Yes Basic, CPRI (8B/10B), HDMI, SDI, DisplayPort, JESD204B/C SATA, GPON 5, Fibre Channel, Interlaken
3 The hardened USB 3.1 IP controller resides in the HPS block, and is supported for devices with GTS transceiver and HPS only. Refer to the Agilex™ 5 Hard Processor System Technical Reference Manual for implementation details of USB3.1.
4 The current release of the Quartus® Prime Pro Edition software does not support this feature.
5 SATA and GPON mode are not supported in the current release of the Quartus® Prime Pro Edition software.