GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.10.2. GTS PMA Register Map

The GTS PMA Register Map consists of the PMA Analog registers, TX PLL counter registers, debug and loopback register information for the GTS PMA lanes.

In order to access GTS PMA registers, you must enable following option in the Avalon® Memory-Mapped Interface tab of the GTS PMA/FEC Direct PHY Intel FPGA IP parameter editor; Enable Avalon® Memory Mapped interface.
Figure 62.  Avalon® Memory-Mapped Interface Parameter Settings For PMA Register Map
Note: You can select the Enable Debug Endpoint on Avalon Interface parameter, if you plan to use the GTS PMA/FEC Direct PHY Intel® FPGA IP debug interconnect fabric to connect the GTS PMA registers with the JTAG interface. Refer to Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP for more information about accessing this Avalon® interface.
Note: When you access the GTS PMA/FEC Direct PHY Intel IP Register Map, you should be aware of the addressing format. The addressing format in the register map file is in a byte addressing format. For example, when you access the registers through System Console, you can use this byte addressing format. You must use the word addressing format (byte address/4) and follow the addressing bit format outlined in MSB Address Bits for Logical Avalon Memory-Mapped Reconfiguration Port Index Value table when you access the registers via Nios® V or the HPS.