GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.4.9. TX and RX PMA and Core Interface FIFO Signals

Table 41.  TX and RX PMA and Core Interface FIFO Signals
Signal Name Clocks Domain/Resets Direction Description
o_tx_pmaif_fifo_empty[(N-1):0] asynchronous output PMA Interface TX FIFO empty.
o_tx_pmaif_fifo_pempty[(N-1):0] asynchronous output PMA Interface TX FIFO partially empty.
o_tx_pmaif_fifo_pfull[(N-1):0] asynchronous output PMA Interface TX FIFO partially full.
o_rx_pmaif_fifo_empty[(N-1):0] asynchronous output PMA Interface RX FIFO empty.
rx_pmaif_fifo_pempty[(N-1):0] asynchronous output PMA Interface RX FIFO partially empty.
o_rx_pmaif_fifo_pfull[(N-1):0] asynchronous output PMA Interface RX FIFO partially full.
o_tx_fifo_full[(N-1):0]

TX Coreclkin

TX Reset

output Core Interface TX FIFO full port.
o_tx_fifo_empty[(N-1):0]

TX Word Clock

Sys PLL Clock

output Core Interface TX FIFO empty port.
o_tx_fifo_pfull[(N-1):0]

TX Coreclkin

TX Reset

output Core Interface TX FIFO partially full port.
o_tx_fifo_pempty[(N-1):0]

TX Word Clock

Sys PLL Clock

output Core Interface TX FIFO partially empty port.
o_rx_fifo_full[(N-1):0]

Transfer clock:

Word Clock

Sys PLL Clock

RX Reset

output Core Interface RX FIFO full port.
o_rx_fifo_empty[(N-1):0]

RX Coreclkin

RX Reset

output Core Interface RX FIFO empty port.
o_rx_fifo_pfull[(N-1):0]

Transfer clock:

Word Clock

Sys PLL Clock

RX Reset

output Core Interface RX FIFO partially full port.
o_rx_fifo_pempty[(N-1):0]

RX Coreclkin

RX Reset

output Core Interface RX FIFO partially empty port.
i_rx_fifo_rd_en[(N-1):0]

RX Coreclkin

RX Reset

input Core Interface RX FIFO read enable port.