GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.8. Asserting reset

The Soft Reset Controller (SRC) together with GTS Reset Sequencer Intel FPGA IP handles all non-PCIe reset scheduling and sequencing for the Agilex™ 5 FPGAs in the PMA Direct and FEC Direct modes. The SRC is automatically instantiated inside the GTS PMA/FEC Direct PHY Intel FPGA IP based on the channels that are used whereas GTS Reset Sequencer Intel FPGA IP is a mandatory IP that you must manually instantiate for your design. Refer to Implementing the GTS Reset Sequencer Intel FPGA IP for more information. Asserting a reset sequence ensures that the PMA in each channel initializes and functions correctly. You can reset the transmitter (TX) and receiver (RX) data paths independently or together.

Figure 53. Reset Top-Level Diagram