GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

2.6.4. Datapath Clock Cadences

The read and write frequency of the PMA FIFO interface determines if you need a standard or custom cadence.
  • Standard cadence: Use if the read and write frequencies of the PMA FIFO interface are the same with 0 ppm frequency delta.
  • Custom cadence: Use if the read and write frequencies of the PMA FIFO interface have different frequencies or have the same frequency but with a frequency delta of greater than 0 ppm.
Table 14.  Supported Datapath Clock Frequencies and Cadences by Datapath Clocking Mode
Datapath Clocking Mode Configuration Datapath Clock Frequency Cadence

PMA clocking mode

(maximum 1 GHz)

PMA Direct

Datapath clock frequency = PMA clock frequency

PMA clock frequency = line rate/PMA width

Use the standard cadence on the TX and RX (data is valid at every clock edge). 19

System PLL clocking mode

(maximum 1 GHz)

PMA Direct

Use Case A: Chip-to-chip applications where the PMA channel and link partner share the same reference clock

Datapath clock frequency ≥ (system PLL output frequency)min where (system PLL output frequency)min = PMA clock frequency

If (system PLL output frequency = PMA clock frequency and ∆ppm = 0), use the standard cadence on the TX and RX (data is valid at every clock edge). Otherwise, use custom cadence. 20 , 21

Use Case B: Applications where the PMA channel and link partner do not share the same reference clock

Datapath clock frequency ≥ (system PLL output frequency)min where (system PLL output frequency)min = (maximum ppm 22 ÷ 1000000 + 1) × PMA clock frequency

System PLL clocking mode

(maximum 1 GHz)

Other configurations with FEC, PCS, and MAC

Datapath clock frequency ≥ (system PLL output frequency)min where (system PLL output frequency)min = PMA clock frequency

For example, for 10GbE-1, use ≥ 322.265625 MHz; and for 25GbE-1, use ≥ 805.6640625 MHz.

If (system PLL output frequency = PMA clock frequency), use the standard cadence on the TX and RX (data is valid at every 32 of 33 or 34 clock cycles). Otherwise, use custom cadence. 23

Refer to Supported PMA Data Widths and Date Rates for supported data rates.

Example of PMA Direct 28.1 Gbps PMA Clocking Mode

  • All blocks between the PMA interface and core interface FIFO are bypassed and all enabled blocks run on the PMA clock.
  • On the transmitter, the TX PMA interface FIFO is clocked by the TX PMA clock on both sides.
  • On the receiver, the RX PMA interface FIFO is clocked by the RX recovered clock on both sides.
  • Use the standard cadence. Data on the TX and RX is valid at every clock edge of the PMA clock.
Figure 31. Example of PMA Direct 28.1 Gbps PMA Clocking Mode

Example of 10 Gbps Ethernet with MAC and PCS Blocks Using Overclocked System Clocking Mode

  • The blocks of the core interface FIFO, Ethernet hard IP MAC and PCS, and the PMA interface FIFO are clocked by the system PLL.
  • On the transmitter, the TX PMA interface FIFO performs a clock transfer from the system PLL domain to the TX PMA clock domain.
  • On the receiver, the RX PMA interface FIFO performs a clock transfer from the RX recovered clock domain to the system PLL domain.
  • Because the system PLL clock frequency is faster than the PMA clock frequency, datapath clocking is overclocked. Therefore, you must use custom cadence.
Figure 32. Example of 10 Gbps Ethernet with MAC and PCS Blocks Using Overclocked System Clocking Mode
19 The TX PMA and TX digital blocks use a PMA clock derived from the local clock. The RX PMA and RX digital blocks run on a recovered clock (the link partner clock).
20 Use Case A: Standard cadence can be used only when the TX PMA reference clock, system PLL reference clock, and link partner TX reference clock are coming from same clock source (with a 0 ppm frequency delta).
21 Use Case B: The system PLL frequency must be overclocked to compensate for a frequency delta of greater than 0 ppm between the TX PMA reference clock, system PLL reference clock, and link partner TX reference clock.
22

maximum ppm = maximum ∆ppm ÷ 2

maximum ∆ppm = max(∆ppm between the link partner TX (the recovered clock on the local RX) and system PLL, ∆ppm between the system PLL and TX PMA)

23 The data path clock is already overclocked compared to the PMA clock by approximately 3% because of PCS and FEC overhead. Therefore, a frequency delta of greater than 0 ppm between the TX PMA reference clock, system PLL reference clock, and link partner TX reference clock is allowed.