Visible to Intel only — GUID: blm1684436053821
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Visible to Intel only — GUID: blm1684436053821
Ixiasoft
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
To generate the example design you need to open the GTS PMA/FEC Direct PHY Intel FPGA IP and go to the Example Design tab. The GTS PMA/FEC Direct PHY Intel FPGA IP parameter editor includes the Generate Example Design function to easily create and generate simulation files to simulate a GTS PMA or FEC direct mode example design.
Example Design Options | Description |
---|---|
1 x 10.3125G FEC Direct Mode (System PLL Clocking) | One NRZ Firecode FEC Direct GTS lane, with a throughput of 10.3125 Gbps, with System PLL clocking mode |
1 x 10.3125G RSFEC Direct Mode (System PLL Clocking) | One NRZ RS-FEC FEC Direct GTS lane, with a throughput of 10.3125 Gbps, with System PLL clocking mode |
1 x 17.16G RSFEC Direct Mode (System PLL Clocking) | One NRZ RS-FEC FEC Direct GTS lane, with a throughput of 17.160 Gbps, with System PLL clocking mode |
1 x 17.16G PCS Direct Mode (System PLL Clocking) | One NRZ PCS Direct GTS lane, with a throughput of 17.160 Gbps, with System PLL clocking mode |
1 x 10.3125G PMA Direct Mode (System PLL Clocking) with Custom Cadence | One NRZ PMA Direct GTS lane, with a throughput of 10.3125 Gbps, with System PLL clocking mode and custom cadencing |
4 x 10.3125G PMA Direct Mode (PMA Clocking) | Four NRZ PMA Direct GTS lane, with 10.3125 Gbps per PMA lane, with PMA clocking mode |
1 x 1G PMA Direct Mode (System PLL Clocking) with Custom Cadence | One NRZ PMA Direct GTS lane, with a throughput of 1Gbps, with System PLL clocking mode and custom cadencing |
1 x 3.125G PMA Direct Mode (System PLL Clocking) with Custom Cadence | One NRZ PMA Direct GTS lane, with a throughput of 3.125 Gbps, with System PLL clocking mode and custom cadencing. |
1 x 28.1G Fire code FEC Direct Mode (System PLL Clocking) | One NRZ Firecode FEC Direct GTS lane, with a throughput of 28.1 Gbps, with System PLL clocking mode. |
1 x 28.1G RSFEC Direct Mode (System PLL Clocking) | One NRZ RS-FEC FEC Direct GTS lane, with a throughput of 28.1 Gbps, with System PLL clocking mode. |
1 x 28.1G PMA Direct Mode (System PLL Clocking) | One NRZ PMA Direct GTS lane, with a throughput of 28.1 Gbps, with System PLL clocking mode. |
1 x 28.1G PMA Direct Mode (PMA Clocking) | One NRZ PMA Direct GTS lane, with a throughput of 28.1 Gbps, with PMA clocking mode. |
- Go to the Example Design tab in the GTS PMA/FEC Direct PHY Intel FPGA IP.
- Select one of the example designs from the drop-down menu. If you select None you cannot generate the example design.
- Click the Acknowledgment option box. This option is to remind you that only the example design you specify in the drop-down menu is generated. If you make any modification to the parameter settings of the IP after selecting the Example Design options from the drop down list, the changes you make to the IP parameters do not take effect. Only the parameters defined for the Example Design options in Example Design Options table take effect. If you do not check the acknowledgment box, you cannot generate the example design.
- If you are using Agilex™ 5 FPGA premium development kit, you can select the board Intel Agilex™ 5 FPGA E-Series 065B Premium Development Kit (ES1) in the drop-down list. With this selection, the Quartus® Prime Pro Edition software generates the example design with the reference clock and channel pin assignments in the .qsf file.
- Ensure steps 2. and step 3. are done, then click Generate Example Design. Clicking Generate Example Design completes the IP Generation. An example design folder is generated containing the Quartus® Prime software project (.qpf), settings (.qsf), and IP files. In addition, there are two folders created named rtl and testbench containing the RTL and simulation testbench files in the following location:
<Project Folder>/<directphy_example_design/example_design>