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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. PCS Direct Signals: IEEE
3.4.6. PCS Direct Signals: IEEE_FLEXE_66/PCS66
3.4.7. Custom Cadence Control and Status Signals
3.4.8. RX PMA Status Signals
3.4.9. TX and RX PMA and Core Interface FIFO Signals
3.4.10. Avalon Memory-Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
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3.8.6. Run-time Reset Sequence—TX + RX
Figure 56. Run-time Reset Sequence—TX + RX
The figure above illustrates the following run-time TX + RX (Asserting and Deasserting TX and RX together) reset sequence:
- Assert i_tx_reset and i_rx_reset.
- o_rx_ready deasserts, indicating that the RX datapaths are no longer operational.
- o_rx_is_lockedtoref and o_rx_is_lockedtodata deassert.
- o_rx_reset_ack asserts, indicating that the RX datapath is fully in reset. o_rx_reset_ack stays asserted until i_rx_reset deasserts.
- o_tx_ready deasserts, indicating that the TX datapaths are no longer operational.
- o_tx_pll_locked deasserts.
- o_tx_reset_ack asserts, indicating that the TX datapath is fully in reset. o_tx_reset_ack stays asserted until i_rx_reset deasserts.
- You then deassert i_tx_reset and i_rx_reset.
- o_tx_pll_locked asserts as the PLL locks to the reference clock.
- o_tx_ready asserts.
- o_rx_is_lockedtoref asserts as the CDR locks to the reference clock.
- o_rx_is_lockedtodata asserts as the CDR locks to the recovered data.
- o_rx_ready asserts.
Note: This waveform is to illustrate the sequence of events when you assert and deassert RX and TX at the same time. This is the typical flow, but the sequence may vary based on the reset operation. o_tx_pll_locked, o_rx_is_lockedtoref, and o_rx_is_lockedtodata may have different behavior in simulation.