GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

2.1.6. PLL and Clock Networks

The GTS transceiver bank has two types of highly configurable clock distribution networks that support the TX PLL and CDR in each PMA channel and system PLL:
  • Reference clock – connects physical reference clock pins to TX PLL, RX CDR PLL, and system PLL.
  • Datapath clock – drives PMA and hardened IPs from options of TX PLL (in PMA clocking mode) and system PLL (in system PLL clocking mode).
The GTS transceiver bank also supports:
  • Multiple lane aggregation into a single link with bonding configuration that minimizes skew (from clock, reset, and interface synchronization) across the bonded lanes.
  • A clock pin in each GTS transceiver bank as a receiver recovered clock output to provide a dedicated clock path to external clock cleaner (for example for CPRI applications).