Visible to Intel only — GUID: lnr1666370291233
Ixiasoft
Visible to Intel only — GUID: lnr1666370291233
Ixiasoft
2.6.1.2. PMA Primary PLL Configuration
The Primary PLL configuration can be used for OTN applications, in which you have a group of channels that are configured in fractional mode and you want to change the fractional value dynamically.
In the primary PLL configuration, the reference clock source for the local CDR and the TX PLL of other channels can be sourced from the PMA channel 0 TX PLL in the same GTS transceiver bank. The TX PLL of channel 0 must be in fractional mode and acts as the reference clock to the TX PLL of other channels. The clock source for the RX CDR of all channels is provided by the TX PLL of its own channel. Refer to the following figure for more information.
Refer to Primary PLL configuration in PMA Support for Fractional Mode table for more information about the implementation details.