GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.4.10. Avalon Memory-Mapped Interface Signals

Table 42.   Avalon® Memory-Mapped Interface Signals (Enable Separate Avalon® Interface per PMA = 0)
Signal Name Clocks Domain/Resets Direction Description
i_reconfig_clk Clock Input Reconfiguration Interface Clock. The clock frequency is 100 – 125 MHz.
i_reconfig_reset i_reconfig_clk Input Reconfiguration Interface Reset. Active high reset. You must ensure that this active high reset signal receives a power-on reset to initialize your device.
i_reconfig_address[17+K p:0] i_reconfig_clk Input Reconfiguration Interface Address K p=Ceiling(log2(N)). Upper address bits are for shared PMA decoding if more than one PMA exists.
i_reconfig_byteenable[3:0] i_reconfig_clk Input Reconfiguration Byte Enable. If byteenable[3:0] is 4’b1111, uses 32-bit Dword access; otherwise uses byte access.
i_reconfig_write i_reconfig_clk Input Reconfiguration Write
i_reconfig_read i_reconfig_clk Input Reconfiguration Read
i_reconfig_writedata[31:0] i_reconfig_clk Input Reconfiguration Write data
o_reconfig_readdata[31:0] i_reconfig_clk Output Reconfiguration Read data
o_reconfig_waitrequest i_reconfig_clk Output Reconfiguration Wait Request
o_reconfig_readdatavalid i_reconfig_clk Output Reconfiguration Read Data Valid.
Table 43.   Avalon® Memory-Mapped Interface Signals (Enable Separate Avalon® Interface per PMA = 1 )
Signal Name Clocks Domain/Resets Direction Description
i_reconfig_clk<n> Clock Input Reconfiguration Interface Clock. The clock frequency is 100 – 125 MHz
i_reconfig_reset<n> i_reconfig_clk<n> Input Reconfiguration Interface Reset. You must ensure that this active high reset signal receives a power-on reset to initialize your device.
i_reconfig_address<n>[17:0] i_reconfig_clk<n> Input Upper address bits are for shared PMA decoding if more than 1 PMA exists.
i_reconfig_byteenable<n>[3:0] i_reconfig_clk<n> Input Byte Enable. If byteenable[3:0] is 4’b1111, uses 32-bit Dword; otherwise uses byte access.
i_reconfig_write<n> i_reconfig_clk<n> Input Reconfiguration Write
i_reconfig_read<n> i_reconfig_clk<n> Input Reconfiguration Read
i_reconfig_writedata<n>[31:0] i_reconfig_clk<n> Input Reconfiguration Write data
o_reconfig_readdata<n>[31:0] i_reconfig_clk<n> Output Reconfiguration Read data
o_reconfig_waitrequest<n> i_reconfig_clk<n> Output Reconfiguration Wait Request
o_reconfig_readdatavalid<n> i_reconfig_clk<n> Output Reconfiguration Read Data Valid.