Visible to Intel only — GUID: frh1682712771719
Ixiasoft
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. PCS Direct Signals: IEEE
3.4.6. PCS Direct Signals: IEEE_FLEXE_66/PCS66
3.4.7. Custom Cadence Control and Status Signals
3.4.8. RX PMA Status Signals
3.4.9. TX and RX PMA and Core Interface FIFO Signals
3.4.10. Avalon Memory-Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
Visible to Intel only — GUID: frh1682712771719
Ixiasoft
3.4.10. Avalon Memory-Mapped Interface Signals
Signal Name | Clocks Domain/Resets | Direction | Description |
---|---|---|---|
i_reconfig_clk | Clock | Input | Reconfiguration Interface Clock. The clock frequency is 100 – 125 MHz. |
i_reconfig_reset | i_reconfig_clk | Input | Reconfiguration Interface Reset. Active high reset. You must ensure that this active high reset signal receives a power-on reset to initialize your device. |
i_reconfig_address[17+K p:0] | i_reconfig_clk | Input | Reconfiguration Interface Address K p=Ceiling(log2(N)). Upper address bits are for shared PMA decoding if more than one PMA exists. |
i_reconfig_byteenable[3:0] | i_reconfig_clk | Input | Reconfiguration Byte Enable. If byteenable[3:0] is 4’b1111, uses 32-bit Dword access; otherwise uses byte access. |
i_reconfig_write | i_reconfig_clk | Input | Reconfiguration Write |
i_reconfig_read | i_reconfig_clk | Input | Reconfiguration Read |
i_reconfig_writedata[31:0] | i_reconfig_clk | Input | Reconfiguration Write data |
o_reconfig_readdata[31:0] | i_reconfig_clk | Output | Reconfiguration Read data |
o_reconfig_waitrequest | i_reconfig_clk | Output | Reconfiguration Wait Request |
o_reconfig_readdatavalid | i_reconfig_clk | Output | Reconfiguration Read Data Valid. |
Signal Name | Clocks Domain/Resets | Direction | Description |
---|---|---|---|
i_reconfig_clk<n> | Clock | Input | Reconfiguration Interface Clock. The clock frequency is 100 – 125 MHz |
i_reconfig_reset<n> | i_reconfig_clk<n> | Input | Reconfiguration Interface Reset. You must ensure that this active high reset signal receives a power-on reset to initialize your device. |
i_reconfig_address<n>[17:0] | i_reconfig_clk<n> | Input | Upper address bits are for shared PMA decoding if more than 1 PMA exists. |
i_reconfig_byteenable<n>[3:0] | i_reconfig_clk<n> | Input | Byte Enable. If byteenable[3:0] is 4’b1111, uses 32-bit Dword; otherwise uses byte access. |
i_reconfig_write<n> | i_reconfig_clk<n> | Input | Reconfiguration Write |
i_reconfig_read<n> | i_reconfig_clk<n> | Input | Reconfiguration Read |
i_reconfig_writedata<n>[31:0] | i_reconfig_clk<n> | Input | Reconfiguration Write data |
o_reconfig_readdata<n>[31:0] | i_reconfig_clk<n> | Output | Reconfiguration Read data |
o_reconfig_waitrequest<n> | i_reconfig_clk<n> | Output | Reconfiguration Wait Request |
o_reconfig_readdatavalid<n> | i_reconfig_clk<n> | Output | Reconfiguration Read Data Valid. |