GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

2.1.7. Avalon® Memory-Mapped Interface

Each GTS transceiver channel has an Avalon® memory-mapped interface for accessing the control and status registers (CSRs) for GTS transceiver building blocks except PCIe Hard IP. The PCIe Hard IP has a PCIe sideband streaming interface to access the CSR registers.

The Avalon® memory-mapped interface also enables access to dynamically reconfigure a subset of PMA channels and hard IP blocks to operate in different modes.