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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. PCS Direct Signals: IEEE
3.4.6. PCS Direct Signals: IEEE_FLEXE_66/PCS66
3.4.7. Custom Cadence Control and Status Signals
3.4.8. RX PMA Status Signals
3.4.9. TX and RX PMA and Core Interface FIFO Signals
3.4.10. Avalon Memory-Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
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6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
Follow these steps to simulate the testbench:
Figure 85. Steps to Simulate the Example Design
- At the command prompt, change to the testbench simulation directory <example_design/testbench>.
cd <directphy_example_design>/example_design/testbench
- Run the simulation using the supported simulators by executing the simulation script file. To simulate with VCS* MX, change to the example_design/testbench directory and the launch the simulation using the shell script:
sh run_vcsmx.sh
Note: For VCS* MX simulations, the simulator generates a synopsys/vcsmx folder upon a successful simulation run. You have to generate the simulation waveform from the synopsys/vcsmx folder.To run the simulation in QuestaSim* , run the following command:vsim -c -do run_vsim.tcl
To run the simulation in Xcelium* , run the following command:sh run_xcelium.sh
Note: Currently the VCS* MX, QuestaSim* , and Xcelium* simulators are supported - The following steps show the simulation testbench flow for the example design:
- Assert resets i_tx_reset and i_rx_reset to reset the IP.
- Wait until resets are acknowledged, when o_tx_reset_ack and o_rx_reset_ack go high.
- Deassert the resets, i_tx_reset and i_rx_reset. Monitor o_tx_ready bit is set to 1, indicating TX path is ready.
- Monitor o_rx_ready bit is set to 1, indicating the RX path is ready.
- Monitor o_tx_pll_locked bit is set to 1, indicating that the TX PLL is locked to reference clock within the PPM threshold status signal.
- Monitor o_rx_is_lockedtoref bit is set to 1, indicating the CDR is frequency locked to reference clock within the PPM threshold.
- Monitor o_rx_is_lockedtodata bit is set to 1, indicating indicates that the CDR is in locked-to-data mode.
- Monitor tx_clkout_freq_valid bit is set to 1, indicating TX clock output frequency is within the upper and lower limits as expected in the definition file.
- Monitor rx_clkout_freq_valid bit is set to 1, indicating RX clock output frequency is within the upper and lower limits as expected in the definition file.
- Monitor verifier_lock bit is set to 1, indicating that the lock to the RX data pattern after successfully predicting 16 consecutive patterns in RX data.
- Monitor verifier_error bit is not set to 1. If it is 1, this indicates the RX data is different than the expected result.
- Analyze the results, a passing testbench displays the following messages in the simulation window, Test case Passed and Simulation Passed, as shown in the following figures.
Figure 86. Sample Results for the PMA Direct PHY Example Design TestbenchFigure 87. Sample Results for the FEC Direct PHY Example Design Testbench