GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design

For successful compilation, you must ensure the following connections are made correctly:
  1. Instantiate all the IPs below in the top level file.
    • GTS PMA/FEC Direct PHY Intel FPGA IP
    • GTS System PLL Clocks Intel FPGA IP
    • GTS Reset Sequencer Intel FPGA IP
  2. Connect port i_refclk of the GTS System PLL Clocks Intel FPGA IP to the port i_rx_cdr_refclk and i_tx_pll_refclk of the GTS PMA/FEC Direct PHY Intel FPGA IP. You must also ensure the source of the reference clock is coming from the same clock.
  3. Connect port o_pma_cu_clk of the GTS Reset Sequencer Intel FPGA IP to port i_pma_cu_clk of the GTS PMA/FEC Direct PHY Intel FPGA IP.
  4. Run all stages as shown in the figure below:
    Figure 88. Example Design Compilation Flow