GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.4.3. Reset Signals

Table 35.  Reset Signals
Signal Name Clocks Domains Direction Description
i_tx_reset asynchronous input TX reset input for TX PMA and TX datapath. Must be kept asserted until o_tx_reset_ack is asserted.
i_rx_reset asynchronous input RX reset input for RX PMA and RX datapath. Must be kept asserted until o_rx_reset_ack is asserted.
o_tx_reset_ack asynchronous output TX fully in reset indicator. o_tx_reset_ack indicates that the PMA is in reset. It asserts after the assertion of i_tx_reset, and deasserts after the deassertion of i_tx_reset.
o_rx_reset_ack asynchronous output RX fully in reset indicator. o_rx_reset_ack indicates that the PMA is in reset. It asserts after the assertion of i_rx_reset and deasserts after the deassertion of i_rx_reset.
o_tx_ready asynchronous output Status port to indicate when TX PMA and TX datapath are reset successfully and ready for data transfer.
o_rx_ready asynchronous output

Status port to indicate when RX PMA and RX datapath are reset successfully and ready for data transfer.

o_tx_am_gen_start 35 asynchronous output When using FEC, indicates when to start sending alignment markers. This clears after i_tx_am_gen_2x_ack is asserted.
i_tx_am_gen_2x_ack 35 tx_coreclkin input When using FEC, you must assert this signal when o_tx_am_gen_start is asserted.
o_src_rs_req[N-1:0] asynchronous output Request signal from Soft Reset Controller (SRC) to GTS Reset Sequencer Intel FPGA IP for reset operation. Asserts when there is a request to toggle reset.
i_src_rs_grant [N-1:0] asynchronous input Grant signal from GTS Reset Sequencer Intel FPGA IP to SRC. Asserts when the reset request is granted by Reset Sequencer Intel FPGA IP.
i_pma_cu_clk[M-1:0] clock input

PMA Control Unit clock source, one per GTS bank for each side of the device. This clock port must be connected from the GTS Reset Sequencer Intel FPGA IP.

35 This signal is only valid for RS-FEC.