GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.4.1. TX and RX Parallel and Serial Interface Signals

Table 33.  TX and RX Parallel and Serial Interface SignalsRefer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for variable definitions.
Signal Name Clocks Domain/Resets Direction Description
i_tx_parallel_data[(80 * N)-1:0]

tx_coreclkin

tx_reset

input Parallel data bus from FPGA core to Agilex™ 5 interface. Some bits map to specific functionality, as Parallel Data Mapping Information describes.
o_rx_parallel_data[(80 * N)-1:0]

rx_coreclkin

rx_reset

output Parallel data bus from FPGA core to Agilex™ 5 interface. Some bits map to specific functionality, as TX and RX Parallel Data Mapping Information for Different Configurations describes.
o_tx_serial_data[N-1:0] tx_reset output TX serial data port. You must assign the port to a TX serial data pin.
o_tx_serial_data_n[N-1:0] tx_reset output Differential pair for TX serial data port.
i_rx_serial_data[N-1:0] rx_reset input RX serial data port. You must assign the port to a RX serial data pin.
i_rx_serial_data_n[N-1:0] rx_reset input Differential pair for RX serial data port.