GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

2.6.1. Reference Clock Network

There are two types of clock lines in the reference clock network; local and regional reference clock lines. For every GTS transceiver bank, there are two independent differential reference clock input pins. The following figure shows the reference clock network and reference clock input pins for GTS transceiver banks.
Figure 22. Reference Clock Network for Devices with Multiple GTS Transceiver Banks on a Side

The first is the local reference clock, which can reach any channel in the same GTS transceiver bank and the system PLL. This local reference clock pin is bi-directional, except on devices with a single GTS transceiver bank on a side, where it serves as an input only reference clock pin. You can configure this bi-directional pin as an output for the CDR recovered clock from any of the four channels in the GTS transceiver bank. In one of the transceiver banks of the device, there is an additional output only pin of this type. The bank location where this output only CDR recovered clock resides varies across the different device variants. You can find the bank location of the CDR recovered clock output pins in the device pinout files.

The second available input reference clock pin is the regional reference clock. This reference clock can be used to feed all the channels and system PLLs in the two closest GTS transceiver banks above or below its own bank. For example, in a four GTS transceiver bank device, the regional reference clock pin in bank 0 can be used in bank 1 and bank 2 as well. However, bank 3 is out of reach of the regional reference clock pin in bank 0.

Additionally, the system PLL can also get its input reference clock from outside the GTS transceiver bank. Adjacent to the GTS transceiver bank, there is a high voltage IO (HVIO) bank. There are 4 single-ended input reference clock pins in the HVIO bank that can be used by the system PLL as a secondary option for the reference clock input source.
Table 12.  Reference Clock Source Comparison
Description Local Reference Clock Regional Reference Clock HVIO Reference Clock
Used by PMA and system PLL PMA and system PLL System PLL
Reach All PMA channels and system PLL within a GTS transceiver bank All PMA channels and system PLL in the two closest GTS transceiver banks above or below its own bank. All system PLLs on the same side of device
Recovered clock output Available Not available Not available
Input/Output Bi-directional, either:
  • Input reference clock
  • Output recovered clock
Input only Input only
Pin location GTS Transceiver bank GTS Transceiver bank HVIO5B or HVIO6A bank
Signal type Differential Differential Single ended
The PMA (TX PLL and CDR) reference clock sources are:
  • Local reference clock input
  • Regional reference clock input (from same GTS transceiver bank or from the neighboring GTS transceiver banks along the same side of the device)
System PLL reference clock sources are:
  • Local reference clock input
  • Regional reference clock input (from same GTS transceiver bank or from the neighboring GTS transceiver banks along the same side of the device)
  • Dual purpose single ended pins (up to four) from HVIO5B or HVIO6A banks.

The CDR in any one of the four PMA channels within the GTS transceiver bank can send the recovered clock externally, for example to feed an external jitter cleaner. The output recovered clock is fed externally through the bi-directional local reference clock pin. The input reference clock is not available when this pin is being used for the recovered clock. In this scenario, the reference clock can come from any of the regional reference clock lines.

In addition to the bidirectional local reference clock pin, there is one additional dedicated CDR clock out pin in one of the GTS transceiver banks. You can use this pin to drive out the recovered clock. You must use this pin if you are planning to migrate to the smallest device variant in the future. This is because devices with a single GTS transceiver bank on a side have a slightly different clock network. Refer to Single GTS Transceiver Bank Device for more information.

If you plan to migrate your design to Agilex™ 5 D-Series FPGAs, refer to the Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs D-Series (Intel RDC item #827018).