GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.8.6. Run-time Reset Sequence—TX + RX

Figure 56. Run-time Reset Sequence—TX + RX

The figure above illustrates the following run-time TX + RX (Asserting and Deasserting TX and RX together) reset sequence:

  1. Assert i_tx_reset and i_rx_reset.
  2. o_rx_ready deasserts, indicating that the RX datapaths are no longer operational.
  3. o_rx_is_lockedtoref and o_rx_is_lockedtodata deassert.
  4. o_rx_reset_ack asserts, indicating that the RX datapath is fully in reset. o_rx_reset_ack stays asserted until i_rx_reset deasserts.
  5. o_tx_ready deasserts, indicating that the TX datapaths are no longer operational.
  6. o_tx_pll_locked deasserts.
  7. o_tx_reset_ack asserts, indicating that the TX datapath is fully in reset. o_tx_reset_ack stays asserted until i_rx_reset deasserts.
  8. You then deassert i_tx_reset and i_rx_reset.
  9. o_tx_pll_locked asserts as the PLL locks to the reference clock.
  10. o_tx_ready asserts.
  11. o_rx_is_lockedtoref asserts as the CDR locks to the reference clock.
  12. o_rx_is_lockedtodata asserts as the CDR locks to the recovered data.
  13. o_rx_ready asserts.
Note: This waveform is to illustrate the sequence of events when you assert and deassert RX and TX at the same time. This is the typical flow, but the sequence may vary based on the reset operation. o_tx_pll_locked, o_rx_is_lockedtoref, and o_rx_is_lockedtodata may have different behavior in simulation.