AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

1.5. What is the AXI Streaming Intel® FPGA IP for PCI Express* ?

The AXI Streaming Intel® FPGA IP for PCI Express* supports PCI Express* Gen3, Gen4, and Gen5 in Endpoint mode. It includes the PCIe* Hard IP (HIP) and HIP Interface Adaptor that converts the native Hard IP interface to an AXI-ST interface. It allows you to choose various blocks and integrate with other Intel FPGA PCI Express IPs like MCDMA based on the application requirement. The IP provides you the flexibility and control over the transaction layer packets by providing parametrization capabilities, functional modes, optional interfaces, error reporting, and debug capabilities. It implements basic telemetry functionality as well.

The figure below shows the block diagram of the AXI Streaming Intel® FPGA IP for PCI Express* . This document covers functional mode description, parameterization, and interface definitions for the IP and its various modes.

Figure 2.  AXI Streaming Intel® FPGA IP for PCI Express* Block Diagram

Refer to the IP Architecture and Functional Description chapter for details on each of the blocks.