AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

1.6. Example Use Models

The AXI Streaming Intel® FPGA IP for PCI Express* can be used in various applications such as an endpoint, virtualization, inline processing, lookaside memory processing, etc. to move data between the source and destination.

The following figure shows a simple block diagram of the IP in Endpoint mode connected to a root port on a host. You can run an application like the Programmable Input Output (PIO) to perform writes/reads to the host memory.

Figure 3. Example of the Programmable Input Output (PIO) Example Using the AXI Streaming Intel® FPGA IP for PCI Express*

The following figure shows two examples of the IP connected to a processing engine directly using AXI streaming interface. The processing engine can be custom user logic implemented in the FPGA fabric, and can perform functions like DMA, e.g., VirtIO DMA connected to a BaseNIC. It receives data from HOST over AXI streaming interface and sends data towards HOST over AXI streaming interface.

Figure 4. Examples of the Inline Processing Model Using the AXI Streaming Intel® FPGA IP for PCI Express*

The following figure shows an example of the IP interfacing with a Memory controller. The processing engine can be custom user logic implemented in the FPGA fabric and can perform functions like DMA. The IP stores data coming from HOST into external memory. The processing engine then reads this data from external memory and performs required operations. Similarly, data coming from other IO devices are stored by the processing engine into external memory. If the processing engine wishes to transfer this data to HOST, it requests the IP to read data from external memory and send it to HOST using the command interface.

Figure 5. Example of Lookaside Memory Processing Model Using the AXI Streaming Intel® FPGA IP for PCI Express*