GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP

The following chapters describe the implementation of GTS transceiver physical (PHY) layer IP, PLLs and clock networks. Refer to the chapters for implementation details of IP instantiation, connection, and simulation, and placement of the GTS transceivers.

Implementation of GTS PMA/FEC PHY designs involves instantiation and connection of the following required and optional Intel FPGA IPs that are available in the Quartus® Prime IP catalog:

  • GTS PMA/FEC Direct PHY Intel FPGA IP (Required)
  • GTS System PLL Clocks Intel FPGA IP (Required only if using system PLL clocking mode)
  • GTS Reset Sequencer Intel FPGA IP (Required)

This user guide organizes the information into the following chapters describing the IP and implementation:

  • Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP — describes functions, parameters, and ports, bit mapping, core clocking, reset and bonding of the IP.
  • Implementing the GTS System PLL Clocks Intel FPGA IP — describes the function, parameters, and ports of the IP.
  • Implementing the GTS Reset Sequencer Intel FPGA IP — describes the function parameters and ports of the IP.
  • GTS PMA/FEC Direct PHY Design Implementation — describes instantiation, connection, simulation and interface planning using an example design.