Visible to Intel only — GUID: azy1681411934296
Ixiasoft
Visible to Intel only — GUID: azy1681411934296
Ixiasoft
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
The following chapters describe the implementation of GTS transceiver physical (PHY) layer IP, PLLs and clock networks. Refer to the chapters for implementation details of IP instantiation, connection, and simulation, and placement of the GTS transceivers.
Implementation of GTS PMA/FEC PHY designs involves instantiation and connection of the following required and optional Intel FPGA IPs that are available in the Quartus® Prime IP catalog:
- GTS PMA/FEC Direct PHY Intel FPGA IP (Required)
- GTS System PLL Clocks Intel FPGA IP (Required only if using system PLL clocking mode)
- GTS Reset Sequencer Intel FPGA IP (Required)
This user guide organizes the information into the following chapters describing the IP and implementation:
- Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP — describes functions, parameters, and ports, bit mapping, core clocking, reset and bonding of the IP.
- Implementing the GTS System PLL Clocks Intel FPGA IP — describes the function, parameters, and ports of the IP.
- Implementing the GTS Reset Sequencer Intel FPGA IP — describes the function parameters and ports of the IP.
- GTS PMA/FEC Direct PHY Design Implementation — describes instantiation, connection, simulation and interface planning using an example design.
Section Content
IP Overview
Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
Signal and Port Reference
Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
Clocking
Custom Cadence Generation Ports and Logic
Asserting reset
Bonding Implementation
Configuration Register
Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
Configurable Quartus Prime Software Settings
Hardware Configuration Using the Avalon Memory-Mapped Interface