GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.7. Custom Cadence Generation Ports and Logic

When using system PLL clocking mode, you must enable the Custom cadence generation (CCG) ports and logic parameter for the use cases that the Custom Cadence Generation Ports and Logic Use Cases table below describes. Enabling CCG logic ensures that the TX PMA interface FIFO does not overflow due to the over clocking of the datapath when using system PLL clocking mode.

Table 56.  Custom Cadence Generation Ports and Logic Use Cases
Configuration Datapath Clocking mode System PLL Frequency Enable Custom Cadence Generation (CCG) Ports and Logic
PMA Direct PMA N/A No
PMA Direct System PLL Equal to PMA parallel clock frequency. No PPM between PMA parallel clock frequency and system PLL frequency. That is, the same reference clock source for PMA and system PLL.38 No
PMA Direct System PLL Greater than the PMA parallel clock frequency. Yes
FEC Direct System PLL Equal to the PMA Parallel clock frequency. No PPM between PMA parallel clock frequency and system PLL frequency. That is, the same reference clock source for PMA and system PLL. No
FEC Direct System PLL Equal to the PMA Parallel clock frequency. PPM between PMA parallel clock frequency and system PLL frequency. That is, different reference clock for PMA and system PLL. Yes
FEC Direct System PLL Greater than the PMA parallel clock frequency. Yes
When you enable Custom cadence generation (CCG) ports and logic, the o_tx_cadence, i_tx_cadence_fast_clk, and i_tx_cadence_slow_clk ports are available in the GTS PMA/FEC Direct PHY Intel FPGA IP. CCG logic uses the i_tx_cadence_fast_clk and i_tx_cadence_slow_clk inputs (does not monitor PMA Interface FIFO status), and generates a o_tx_cadence output signal. You must use o_tx_cadence to assert and de-assert the TX PMA Interface data valid bit. This bit is one of the bits in TX parallel data. Refer to Parallel Data Mapping Information.
Table 57.  tx_cadence_fast_clk and tx_cadence_slow_clk connections
Configuration Enable TX Double Width Transfer Recommended Connections
PMA Direct Yes
  • Connect i_tx_cadence_fast_clk to System PLL Clock Div2
  • Connect i_tx_cadence_slow_clk to word clock / 2
PMA Direct No
  • Connect i_tx_cadence_fast_clk to System PLL Clock
  • i_tx_cadence_slow_clk to word clock
FEC Direct Yes
  • Connect i_tx_cadence_fast_clk to System PLL Clock Div2
  • i_tx_cadence_slow_clk to User Clock (DIV 66 or DIV 68)
38 When using PMA direct with system PLL clocking mode, if the reference clock for PMA and system PLL are from different clock source, then the system PLL frequency cannot be equal to the PMA parallel clock frequency. System PLL frequency must be greater than or equal to the fastest possible TX and RX PMA clock, including PPM.