GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.10. Configuration Register

Each GTS transceiver channel has an Avalon® memory-mapped interface for reconfiguration. You can access the GTS PMA/FEC Direct PHY Intel FPGA IP soft CSRs and the GTS PMA registers using the same Avalon® memory-mapped interface.

Here are the key considerations for the configuration registers:
  • Write operations to a read-only register field have no effect.
  • Write operations to reserved registers have an undefined effect. You must not write to reserved registers.
  • Read operations that address a reserved register return an unspecified result.
  • Accesses to registers that do not exist in your IP core variation, or to register bits that your IP core variation does not define, have an unspecified result. You must consider these registers and register bits reserved.
  • Although you can only access registers in 32-bit read and write operations, do not attempt to write or ascribe meaning to values in undefined register bits.
The GTS PMA register map contains the reconfiguration register information for:
  • PMA and FEC Direct PHY soft CSR registers
  • GTS PMA registers
The following sections describe the register map for each area and how to access the registers.