GTS Transceiver PHY User Guide

ID 817660
Date 10/07/2024
Public
Document Table of Contents

3.5. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath

The tx_paallel_data bit ad x_paallel_data bit width depeds o the PMA width ad Numbe of PMA laes IP paametes. Use the followig equatio to detemie the total tx_paallel_data o x_paallel_data bit width:

Total tx_paallel_data o x_paallel_data Bit Width Equatio:

tx/x_paallel_data[(80*N)-1:0]

Whee:

  • N = Numbe of PMA laes value fom 1 to 4.

The tx/x_paallel_data sigals iclude the valid paallel data bits ad othe fuctioality bits, such as the data valid bit, the wite eable fo TX coe iteface FIFO i elastic mode bit, the RX deskew bit, ad the aligmet make bits (fo FEC mode). These sigals tavel to ad fom the FPGA fabic to the tasceive block, ad ae clocked by the same paallel clock. This paallel clock ca be a PMA clock o System PLL clock.

Example 1: Total tx/x_paallel_data Bit Width with 2 PMA Laes (N=2) ad 8-bit PMA Width (X=1)

tx_paallel_data [(80*2)-1:0] = tx_paallel_data [159:0]
x_paallel_data [(80*2)-1:0] = x_paallel_data [159:0]

Paallel Data Mappig ifomatio fo TX ad RX

Table 47.  Vaiable Defiitios
Vaiable Values Desciptio
N 1, 2, 4, 6, 8 Numbe of laes
0 to N-1 N is the PMA idex umbe
D D = PMA Width D is the data width value to calculate the total paallel data bits
Table 48.  PMA Diect Mode Paallel Data Calculatios
PMA Cofiguatio MSB LSB TX Paallel Data RX Paallel Data

PMA Width = 8, 10, 16, 20, 32

Sigle Width

79 Wite Eable fo TX Coe FIFO i Elastic Mode 35 Data valid fo RX Coe FIFO i Elastic Mode35
38 + (80*) TX PMA Iteface Data Valid RX PMA Iteface Data Valid
[D-1] + (80*) 0 + (80*) TX Data RX Data

PMA Width = 8, 10, 16, 20, 32

Double Width

79 Wite Eable fo TX Coe FIFO i Elastic Mode35 Data valid fo RX Coe FIFO i Elastic Mode35
(40+D-1) + (80*) 40 + (80*) TX Data (Uppe Data Bits) RX Data (Uppe Data Bits)
38 + (80*) TX PMA Iteface Data Valid RX PMA Iteface Data Valid
(D -1) + (80*) 0 + (80*) TX Data (Lowe Data Bits) RX Data (Lowe Data Bits)
Table 49.  FEC Diect Mode Paallel Data Calculatios
MSB LSB TX Paallel Data RX Paallel Data
77 Aligmet Make -
72 40 TX Data (Uppe Data Bits) RX Data (Uppe Data Bits)
38 TX PMA Iteface Data Valid Bit RX PMA Iteface Data Valid Bit
37 Aligmet Make Aligmet Make
32 2 TX Data (Lowe Data Bits) RX Data (Lowe Data Bits)
1 0 Syc Head
Table 50.  Example of Bit Mappig of TX Paallel Data Bits fo PMA Diect Mode with PMA Width = 32
N (Numbe of Laes) 1 2 4 TX Paallel Data
Bits 79 159 319

Wite Eable fo TX Coe FIFO i Elastic Mode.

38 118 278 TX PMA Iteface Data Valid
31:0 118:80 271:240 TX Data (Lowe Data Bits)
71:40 151:120 311:280 TX Data (Uppe Data Bits)
Table 51.  PCS Diect Mode — IEEE MII Iteface Paallel Data Calculatios
MSB LSB TX Paallel Data RX Paallel Data
74 i_tx_mii_c[7] o_x_mii_c[7]
73 66 i_tx_mii_d[63:56] o_x_mii_d[63:56]
65 i_tx_mii_c[6] o_x_mii_c[6]
64 57 i_tx_mii_d[55:48] o_x_mii_d[55:48]
56 i_tx_mii_c[5] o_x_mii_c[5]
55 48 i_tx_mii_d[47:40] o_x_mii_d[47:40]
47 i_tx_mii_c[4] o_x_mii_c[4]
46 39 i_tx_mii_d[39:32] o_x_mii_d[39:32]
38 i_tx_mii_valid o_x_mii_valid
37 i_tx_mii_am o_x_mii_am
35 i_tx_mii_c[3] o_x_mii_c[3]
34 27 i_tx_mii_d[31:24] o_x_mii_d[31:24]
26 i_tx_mii_c[2] o_x_mii_c[2]
25 18 i_tx_mii_d[23:16] o_x_mii_d[23:16]
17 i_tx_mii_c[1] o_x_mii_c[1]
16 9 i_tx_mii_d[15:8] o_x_mii_d[15:8]
8 i_tx_mii_c[0] o_x_mii_c[0]
7 0 i_tx_mii_d[7:0] o_x_mii_d[7:0]
Table 52.  TX ad RX Paallel Data to IEEE MII Pot Mappig Sigals fo PCS Diect Mode
     
i_tx_mii_d[63:0] Iput Dive MII ecoded cotol bytes o this iput data bus. i_tx_mii_d[7:0] holds the fist byte the IP coe tasmits
i_tx_mii_c[7:0] Iput Fo each cotol byte dive ito i_tx_mii_d bus, dive the coespodig bit high. Fo example, i_tx_mii_c[0] coespods to i_tx_mii_d[7:0]. If the value of a bit is 1, the coespodig data byte is a cotol byte. Othewise it is data.
i_tx_mii_valid Iput Dive this sigal high to qualify the data o cotol bytes o the i_tx_mii_d bus.
i_tx_mii_am Iput Aligmet make isetio bit (applicable oly fo RS-FEC). Dive this sigal to 0 if Fiecode FEC o FEC is ot eabled.
o_x_mii_d[63:0] Output Receive Etheet fames o MII cotol bytes, MII ecoded, o this iput data bus. o_x_mii_d[7:0] holds the fist byte eceived.
o_x_mii_c[15:0] Output Sample this bus to detemie if o_x_mii_d[63:0] iput bus is cayig cotol o data bytes. If the value of a bit is 1, the coespodig data byte is a cotol byte. If the value of a bit is 0, the coespodig data byte is data.
o_x_mii_valid Output Sample this sigal to qualify the RX MII data, RX MII cotol bits, ad the RX valid aligmet make sigals.
Table 53.  PCS Diect Mode — IEEE_FLEXE_66/PCS66 Paallel Data Calculatios
MSB LSB TX Paallel Data RX Paallel Data
71 39 i_txd[65:33] o_xd[65:33]
38 i_tx_valid o_x_valid
37 i_tx_am o_x_am
32 0 i_txd[32:0] o_xd[32:0]
Table 54.  TX ad RX Paallel Data to IEEE_FLEXE_66/PCS66 Mappig Sigals fo PCS Diect Mode
Sigal Name Diectio Desciptio
i_txd[65:0] Iput Dive this data bus with the 66-bit data blocks fom the souce. The two least sigificat bits ae the heade syc bits. I FlexE mode, the TX PCS scambles the 66-bit data block ad stipes the data blocks acoss the tasceive chaels.
i_tx_valid Iput Dive this sigal high to qualify the 66-bit data block o the i_txd iput data bus.
i_tx_am Iput Dive valid 66-bit data blocks whe this sigal has bee asseted. Do ot dive valid data blocks whe this sigal is deasseted.
o_xd[65:0] Output Output data bus that eceives Etheet fames o MII cotol bytes, MII ecoded. o_xd[7:0] holds the fist byte eceived.
o_x_valid Output PCS66 data valid sigal. The sigal idicates valid data o PCS66 pots.
o_x_am Output Aligmet make idicato (applicable fo RS-FEC). This sigal idicates the blocks cuetly o o_xd have bee idetified as aligmet makes.
35 Oly available fo PMA clockig ad if TX/RX coe FIFO is i elastic mode.