GTS Transceiver PHY User Guide

Download PDF
ID 817660
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. GTS Transceiver Overview 2. GTS Transceiver Architecture 3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP 4. Implementing the GTS System PLL Clocks Intel FPGA IP 5. Implementing the GTS Reset Sequencer Intel FPGA IP 6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 7. Design Assistance Tools 8. Debugging GTS Transceiver Links with Transceiver Toolkit 9. Document Revision History for the GTS Transceiver PHY User Guide
1. GTS Transceiver Overview x
1.1. GTS Transceiver Design Flow
2. GTS Transceiver Architecture x
2.1. Building Blocks 2.2. Channel Placement Rules and Design Requirements 2.3. PMA Architecture 2.4. PCS Architecture 2.5. Forward Error Correction (FEC) Architecture 2.6. Clock Architecture 2.7. Bonding and Deskew
2.1. Building Blocks x
2.1.1. PMA 2.1.2. FEC 2.1.3. PCS 2.1.4. Ethernet MAC 2.1.5. PCI Express* Hard IP 2.1.6. PLL and Clock Networks 2.1.7. Avalon® Memory-Mapped Interface
2.1.1. PMA x
2.1.1.1. Protocol Support Using PMA Direct Mode
2.1.1.1. Protocol Support Using PMA Direct Mode x
2.1.1.1.1. SDI 2.1.1.1.2. HDMI 2.1.1.1.3. DisplayPort 2.1.1.1.4. CPRI
2.2. Channel Placement Rules and Design Requirements x
2.2.1. Hard IP Rules 2.2.2. Use Scenario Rules 2.2.3. Unused PMA Rules 2.2.4. General Design Requirement
2.3. PMA Architecture x
2.3.1. Transmitter PMA Architecture 2.3.2. Receiver PMA Architecture 2.3.3. PMA Loopback Modes
2.3.1. Transmitter PMA Architecture x
2.3.1.1. Transmitter Buffer 2.3.1.2. Serializer 2.3.1.3. Data Pattern Generator and Verifier
2.3.2. Receiver PMA Architecture x
2.3.2.1. Receiver Buffer and Equalizer 2.3.2.2. Deserializer 2.3.2.3. CDR Block 2.3.2.4. PMA Tuning
2.3.2.1. Receiver Buffer and Equalizer x
2.3.2.1.1. Control Unit
2.5. Forward Error Correction (FEC) Architecture x
2.5.1. FEC Loopback Mode
2.6. Clock Architecture x
2.6.1. Reference Clock Network 2.6.2. Datapath Clock Network 2.6.3. System PLL 2.6.4. Datapath Clock Cadences 2.6.5. Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank
2.6.1. Reference Clock Network x
2.6.1.1. Single GTS Transceiver Bank Device 2.6.1.2. PMA Primary PLL Configuration
2.6.3. System PLL x
2.6.3.1. I/O PLLs in HVIO Bank as System PLL 2.6.3.2. Running PCIe* and Non- PCIe* Protocols in a GTS Transceiver Bank 2.6.3.3. System PLL Clock for FPGA Core 2.6.3.4. System PLL with HVIO Reference Clock
2.7. Bonding and Deskew x
2.7.1. Bonding Architecture 2.7.2. TX Deskew Function
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.1. IP Overview 3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP 3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting reset 3.9. Bonding Implementation 3.10. Configuration Register 3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing 3.12. Configurable Quartus® Prime Software Settings 3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. PCS Direct Supported Modes 3.1.4. Unsupported PMA/FEC/PCS Modes
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.3.1. Preset IP Parameter Settings 3.3.2. Common Datapath Options 3.3.3. TX Datapath Options 3.3.4. RX Datapath Options 3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations 3.3.6. FEC Options 3.3.7. PCS Options 3.3.8. Avalon® Memory-Mapped Interface Options 3.3.9. Register Map IP-XACT Support 3.3.10. Analog Parameter Options
3.3.3. TX Datapath Options x
3.3.3.1. TX PMA Interface Parameters
3.3.4. RX Datapath Options x
3.3.4.1. RX PMA Interface Parameters
3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations x
3.3.5.1. PMA Configuration Rules for SDI Mode 3.3.5.2. PMA Configuration Rules for HDMI Mode 3.3.5.3. PMA Configuration Rules for DisplayPort Mode 3.3.5.4. PMA Configuration Rules for CPRI Mode
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. RX PMA Status Signals 3.4.7. TX and RX PMA and Core Interface FIFO Signals 3.4.8. Avalon Memory-Mapped Interface Signals
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. PMA Fractional Mode
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the i_tx_cadence_slow_clk_locked Port
3.8. Asserting reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Run-time Reset Sequence—TX 3.8.5. Run-time Reset Sequence—RX 3.8.6. Run-time Reset Sequence—TX + RX 3.8.7. RX Data Loss/CDR Lock Loss (Auto-Recovery) 3.8.8. TX PLL Lock Loss
3.9. Bonding Implementation x
3.9.1. Bonding Placement Requirements
3.10. Configuration Register x
3.10.1. GTS PMA and FEC Direct PHY Soft CSR Register Map 3.10.2. GTS PMA Register Map 3.10.3. Accessing Configuration Registers
3.10.2. GTS PMA Register Map x
3.10.2.1. Logical Avalon® Memory-Mapped Port Indexing
3.10.3. Accessing Configuration Registers x
3.10.3.1. Accessing GTS PMA and FEC Direct PHY Soft CSR Registers 3.10.3.2. Accessing GTS PMA Registers
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing x
3.11.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP 3.11.2. Using JTAG to Avalon Master Bridge Intel FPGA IP
3.11.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.11.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.11.2. Using JTAG to Avalon Master Bridge Intel FPGA IP x
3.11.2.1. RTL Connection Example for JTAG to Avalon Master Bridge Intel® FPGA IP
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.13.1. Direct Register Method 3.13.2. GTS Attribute Access Method
3.13.1. Direct Register Method x
3.13.1.1. Direct Register Method Examples
3.13.2. GTS Attribute Access Method x
3.13.2.1. GTS Attribute Access Method Example 1 3.13.2.2. GTS Attribute Access Method Example 2
4. Implementing the GTS System PLL Clocks Intel FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for GTS System PLL Clocks Intel FPGA IP Usage 4.5. Guidelines to Indicate System PLL Reference Clock is Ready
4.5. Guidelines to Indicate System PLL Reference Clock is Ready x
4.5.1. Example Flow to Indicate System PLL Reference Clock is Ready
5. Implementing the GTS Reset Sequencer Intel FPGA IP x
5.1. IP Requirements 5.2. IP Parameters 5.3. IP Port List 5.4. GTS Reset Sequencer Intel FPGA IP General Interface 5.5. GTS Reset Sequencer Intel FPGA IP Design Flow 5.6. GTS Reset Sequencer Intel FPGA IP Use Cases
5.6. GTS Reset Sequencer Intel FPGA IP Use Cases x
5.6.1. Example Use Case 1 5.6.2. Example Use Case 2
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design x
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP 6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description 6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench 6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design x
6.2.1. Fast Simulation Support 6.2.2. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Directory Structure
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench x
6.4.1. Modifying the Example Design and Performing Simulation
7. Design Assistance Tools x
7.1. Clocking and Datapath Tool 7.2. TX Equalizer Tool
8. Debugging GTS Transceiver Links with Transceiver Toolkit x
8.1. GTS Transceiver Toolkit Parameter Settings 8.2. GTS Transceiver Toolkit GUI 8.3. GTS Transceiver Debugging Flow Walkthrough
8.2. GTS Transceiver Toolkit GUI x
8.2.1. Collection View
8.3. GTS Transceiver Debugging Flow Walkthrough x
8.3.1. Modifying the Design to Enable GTS Transceiver Debug Toolkit 8.3.2. Programming the Design into an Intel FPGA 8.3.3. Loading the Design to the Transceiver Toolkit 8.3.4. Creating Transceiver Links 8.3.5. Running BER Tests 8.3.6. Running Eye Viewer Tests 8.3.7. Running Link Optimization Tests
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide

9. Document Revision History for the GTS Transceiver PHY User Guide

Documet Vesio Quatus® Pime Vesio Chages
2024.10.07 24.3 Made the followig chages:
  • Coected the Key GTS Tasceive Featues table with the Etheet Techology Cosotium (ETC) FEC amig i the GTS Tasceive Oveview chapte.
  • Added ew figue GTS Tasceive Desig Flow i the GTS Tasceive Oveview chapte.
  • Added figue GTS Tasceive Bak Layout fo E-Seies FPGAs with 8 GTS Tasceives i the Buildig Blocks sectio.
  • Updated ote about FEC suppot fo PCS Diect mode i the Had IP Cofiguatios Suppoted with PMA table.
  • Added ew sectio Potocol Suppot usig PMA Diect Mode with sub-sectios fo SDI, HDMI, DisplayPot ad CPRI potocol suppot ifomatio.
  • Updated the A5E 028 device powe dow suppot bak fo the M16A package i the Selected E-Seies GTS Tasceive Baks that Suppot Powe Dow table.
  • Updated the Data Patte Geeato ad Veifie sectio with ew ifomatio about the built-i PRBS geeato ad veifie.
  • Updated the PCS Achitectue sectio with IEEE 802.3 compliat Clause 107 suppot ad updated amig fo the IEEE MII iteface.
  • Coected the Suppoted FEC Modes ad Compliace Specificatios table with the Etheet Techology Cosotium (ETC) FEC amig i the Fowad Eo Coectio (FEC) Achitectue sectio.
  • Added bodig suppot fo the x6 ad x8 modes fo PCS Diect mode i the Bodig Achitectue sectio.
  • Coected the Etheet Techology Cosotium (ETC) FEC amig i the FEC Diect Suppoted Modes sectio.
  • Updated the PCS Diect Suppoted Modes sectio with simplex ad duplex suppot ad updated amig fo the IEEE MII iteface.
  • Updated suppoted modes i the Usuppoted PMA/FEC/PCS Modes sectio.
  • Updated the Cofiguig the GTS PMA/FEC Diect PHY Itel FPGA IP sectio with Riviea-PRO* simulato suppot.
  • Removed ote fom the Povide sepaate iteface fo each PMA paamete i the Commo Datapath Optios sectio.
  • Added ew sectio PMA Cofiguatio Rules fo Specific Potocol Mode Implemetatio with sub-sectios fo PMA Cofiguatio Rules fo SDI Mode, PMA Cofiguatio Rules fo HDMI Mode, PMA Cofiguatio Rules fo DP Mode ad PMA Cofiguatio Rules fo CPRI Mode potocol modes.
  • Coected the Etheet Techology Cosotium (ETC) FEC amig i the FEC Optios sectio.
  • Updated amig fo the IEEE MII iteface i the PCS Optios sectio.
  • Removed ote fom the Eable sepaate Avalo iteface pe PMA paamete i the Avalo® Memoy-Mapped Iteface Optios sectio.
  • Updated the Aalog Paamete Optios i Paamete Edito figue i the Aalog Paamete Optios sectio.
  • Removed sigals o_tx_am_ge_stat ad i_tx_am_ge_2x_ack fom the Reset Sigals table.
  • Removed the PCS Diect Sigals: IEEE ad PCS Diect Sigals: IEEE_FLEXE_66/PCS66 topics fom the Sigal ad Pot Refeece sectio.
  • Added ew tables TX ad RX Paallel Data to IEEE MII Pot Mappig Sigals fo PCS Diect Mode ad TX ad RX Paallel Data to IEEE_FLEXE_66/PCS66 Mappig Sigals fo PCS Diect Mode i the Bit Mappig fo PMA ad FEC Mode PHY TX ad RX Datapath sectio.
  • Removed sigals o_tx_am_ge_stat ad i_tx_am_ge_2x_ack fom the Reset Sigal Requiemets sectio.
  • Added ote i the Ru-time Reset Sequece—TX topic about RS-FEC mode suppot.
  • Removed the Ru-time Reset Sequece—TX with FEC topic fom the Reset Sigal Requiemets sectio.
  • Added ote about usig the TX Equalize Tool i the TX Equalize Co-efficiets topic i the Diect Registe Method Examples sectio.
  • Added Riviea-PRO* scipt locatio i the GTS PMA/FEC Diect PHY Itel FPGA IP Example Desig Diectoy Stuctue sectio.
  • Added Riviea-PRO* scipt u commad i the Simulatig the GTS PMA/FEC Diect PHY Itel FPGA IP Example Desig Testbech sectio.
  • Added ifomatio about modifyig the example desig pi assigmets i the Hadwae Testig the GTS PMA/FEC Diect PHY Itel FPGA IP Example Desig sectio.
2024.07.08 24.2 Made the followig chages:
  • Added a ote about esticted suppot fo Agilex™ 5 D-Seies FPGAs i the GTS Tasceive Oveview sectio.
  • Updated the Agilex™ 5 D-Seies FPGA package ifomatio i figues i the Buildig Blocks sectio.
  • Added ew table with the Agilex™ 5 D-Seies FPGA powe dow ifomatio i the Uused PMA Rules sectio.
  • Updated the System PLL Clock Netwok figue i the System PLL sectio.
  • Added ew sectio Shaed Clockig Resouces Betwee the GTS Tasceive Bak ad HVIO Bak with ifomatio about shaed clockig esouces.
  • Claified ifomatio i the I/O PLLs i HVIO Bak as System PLL sectio.
  • Added ew sectio PCS Achitectue with ifomatio about PCS diect modes.
  • Updated ifomatio i the FEC Loopback Mode sectio.
  • Added ifomatio about PCS diect mode i the Bodig Achitectue sectio.
  • Updated the IP Oveview sectio with the PCS diect mode ifomatio.
  • Updated the Peset IP Paamete Settigs sectio with the PCS diect mode peset.
  • Updated PMA data ate paamete settig values ad default value i desciptio i the Commo Datapath Optios sectio.
  • Added ew sectio PCS Optios with ifomatio about the PCS diect paamete settigs.
  • Updated the Eable eaddatavalid pot o Avalo® iteface paamete settig i the Avalo® Memoy-Mapped Iteface Optios sectio.
  • Added ew sectio Registe Map IP-XACT Suppot with ifomatio about the egiste map suppot i IP-XACT.
  • Added ew sectio Aalog Paamete Optios with ifomatio about the RX ad TX Aalog paamete settigs.
  • Added additioal desciptio fo the i_tx_pll_efclk_p[N-1:0] ad i_x_cd_efclk_p[N-1:0] sigals i the TX ad RX Refeece Clock ad Clock Output Iteface Sigals table.
  • Added PCS diect mode paallel data calculatios i the Bit Mappig fo PMA ad FEC Mode PHY TX ad RX Datapath sectio.
  • Updated the RX Maual Tuig desciptio i the Cofiguable Softwae Settigs sectio.
  • Updated the egiste map addesses fo TX equalizatio i Logical Avalo Memoy-Mapped Pot Idexig ad Diect Registe Method Examples sectios.
  • Updated the GTS Attibute Access Data Value 1 table with TX to RX paallel loopback data field value.
  • Updated the GTS System PLL Clock Itel FPGA IP Paametes ad Mode of System PLL - System PLL Refeece Clock ad Output Fequecies tables with PCIE_FREQ_500 value settig.
  • Updated the Guidelies fo GTS System PLL Clocks Itel FPGA IP Usage sectio with PCIe* compliace ifomatio.
  • Updated the Implemetig the GTS Reset Sequece Itel FPGA IP chapte itoductio.
  • Updated the GTS Reset Sequece Itel FPGA IP Desig Flow sectio with additioal ifomatio.
  • Updated suppoted simulato fom VCS* to VCS* MX i seveal sectios.
  • Updated the Example Desig Optios table with PCS diect mode ad seveal 28.1 Gbps optios.
  • Updated the Geeatig the GTS PMA/FEC Diect PHY Itel FPGA IP Example Desig sectio with developmet kit boad selectio ifomatio.
  • Updated the GTS PMA/FEC Diect PHY Itel FPGA IP Example Desig Fuctioal Desciptio sectio with the PCS diect mode ifomatio.
  • Added ote i the Simulatig the GTS PMA/FEC Diect PHY Itel FPGA IP Example Desig Testbech sectio about VCS* MX wavefom geeatio.
  • Added ote i the Modifyig the Example Desig ad Pefomig Simulatio sectio about soft eset cotolle simulatio model.
  • Added ew sectio Hadwae Testig the GTS PMA/FEC Diect PHY Itel FPGA IP Example Desig.
  • Updated the Ruig Eye Viewe Tests sectio with ifomatio about the Eye Width measuemets.
  • Updated the Ruig Lik Optimizatio Tests sectio with ifomatio about the Eye Width measuemets.
2024.04.01 24.1 Iitial elease.
Level Two Title