GTS Transceiver PHY User Guide

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ID 817660
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. GTS Transceiver Overview 2. GTS Transceiver Architecture 3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP 4. Implementing the GTS System PLL Clocks Intel FPGA IP 5. Implementing the GTS Reset Sequencer Intel FPGA IP 6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 7. Design Assistance Tools 8. Debugging GTS Transceiver Links with Transceiver Toolkit 9. Document Revision History for the GTS Transceiver PHY User Guide
1. GTS Transceiver Overview x
1.1. GTS Transceiver Design Flow
2. GTS Transceiver Architecture x
2.1. Building Blocks 2.2. Channel Placement Rules and Design Requirements 2.3. PMA Architecture 2.4. PCS Architecture 2.5. Forward Error Correction (FEC) Architecture 2.6. Clock Architecture 2.7. Bonding and Deskew
2.1. Building Blocks x
2.1.1. PMA 2.1.2. FEC 2.1.3. PCS 2.1.4. Ethernet MAC 2.1.5. PCI Express* Hard IP 2.1.6. PLL and Clock Networks 2.1.7. Avalon® Memory-Mapped Interface
2.1.1. PMA x
2.1.1.1. Protocol Support Using PMA Direct Mode
2.1.1.1. Protocol Support Using PMA Direct Mode x
2.1.1.1.1. SDI 2.1.1.1.2. HDMI 2.1.1.1.3. DisplayPort 2.1.1.1.4. CPRI
2.2. Channel Placement Rules and Design Requirements x
2.2.1. Hard IP Rules 2.2.2. Use Scenario Rules 2.2.3. Unused PMA Rules 2.2.4. General Design Requirement
2.3. PMA Architecture x
2.3.1. Transmitter PMA Architecture 2.3.2. Receiver PMA Architecture 2.3.3. PMA Loopback Modes
2.3.1. Transmitter PMA Architecture x
2.3.1.1. Transmitter Buffer 2.3.1.2. Serializer 2.3.1.3. Data Pattern Generator and Verifier
2.3.2. Receiver PMA Architecture x
2.3.2.1. Receiver Buffer and Equalizer 2.3.2.2. Deserializer 2.3.2.3. CDR Block 2.3.2.4. PMA Tuning
2.3.2.1. Receiver Buffer and Equalizer x
2.3.2.1.1. Control Unit
2.5. Forward Error Correction (FEC) Architecture x
2.5.1. FEC Loopback Mode
2.6. Clock Architecture x
2.6.1. Reference Clock Network 2.6.2. Datapath Clock Network 2.6.3. System PLL 2.6.4. Datapath Clock Cadences 2.6.5. Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank
2.6.1. Reference Clock Network x
2.6.1.1. Single GTS Transceiver Bank Device 2.6.1.2. PMA Primary PLL Configuration
2.6.3. System PLL x
2.6.3.1. I/O PLLs in HVIO Bank as System PLL 2.6.3.2. Running PCIe* and Non- PCIe* Protocols in a GTS Transceiver Bank 2.6.3.3. System PLL Clock for FPGA Core 2.6.3.4. System PLL with HVIO Reference Clock
2.7. Bonding and Deskew x
2.7.1. Bonding Architecture 2.7.2. TX Deskew Function
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.1. IP Overview 3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP 3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting reset 3.9. Bonding Implementation 3.10. Configuration Register 3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing 3.12. Configurable Quartus® Prime Software Settings 3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. PCS Direct Supported Modes 3.1.4. Unsupported PMA/FEC/PCS Modes
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.3.1. Preset IP Parameter Settings 3.3.2. Common Datapath Options 3.3.3. TX Datapath Options 3.3.4. RX Datapath Options 3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations 3.3.6. FEC Options 3.3.7. PCS Options 3.3.8. Avalon® Memory-Mapped Interface Options 3.3.9. Register Map IP-XACT Support 3.3.10. Analog Parameter Options
3.3.3. TX Datapath Options x
3.3.3.1. TX PMA Interface Parameters
3.3.4. RX Datapath Options x
3.3.4.1. RX PMA Interface Parameters
3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations x
3.3.5.1. PMA Configuration Rules for SDI Mode 3.3.5.2. PMA Configuration Rules for HDMI Mode 3.3.5.3. PMA Configuration Rules for DisplayPort Mode 3.3.5.4. PMA Configuration Rules for CPRI Mode
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. RX PMA Status Signals 3.4.7. TX and RX PMA and Core Interface FIFO Signals 3.4.8. Avalon Memory-Mapped Interface Signals
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. PMA Fractional Mode
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the i_tx_cadence_slow_clk_locked Port
3.8. Asserting reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Run-time Reset Sequence—TX 3.8.5. Run-time Reset Sequence—RX 3.8.6. Run-time Reset Sequence—TX + RX 3.8.7. RX Data Loss/CDR Lock Loss (Auto-Recovery) 3.8.8. TX PLL Lock Loss
3.9. Bonding Implementation x
3.9.1. Bonding Placement Requirements
3.10. Configuration Register x
3.10.1. GTS PMA and FEC Direct PHY Soft CSR Register Map 3.10.2. GTS PMA Register Map 3.10.3. Accessing Configuration Registers
3.10.2. GTS PMA Register Map x
3.10.2.1. Logical Avalon® Memory-Mapped Port Indexing
3.10.3. Accessing Configuration Registers x
3.10.3.1. Accessing GTS PMA and FEC Direct PHY Soft CSR Registers 3.10.3.2. Accessing GTS PMA Registers
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing x
3.11.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP 3.11.2. Using JTAG to Avalon Master Bridge Intel FPGA IP
3.11.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.11.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.11.2. Using JTAG to Avalon Master Bridge Intel FPGA IP x
3.11.2.1. RTL Connection Example for JTAG to Avalon Master Bridge Intel® FPGA IP
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.13.1. Direct Register Method 3.13.2. GTS Attribute Access Method
3.13.1. Direct Register Method x
3.13.1.1. Direct Register Method Examples
3.13.2. GTS Attribute Access Method x
3.13.2.1. GTS Attribute Access Method Example 1 3.13.2.2. GTS Attribute Access Method Example 2
4. Implementing the GTS System PLL Clocks Intel FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for GTS System PLL Clocks Intel FPGA IP Usage 4.5. Guidelines to Indicate System PLL Reference Clock is Ready
4.5. Guidelines to Indicate System PLL Reference Clock is Ready x
4.5.1. Example Flow to Indicate System PLL Reference Clock is Ready
5. Implementing the GTS Reset Sequencer Intel FPGA IP x
5.1. IP Requirements 5.2. IP Parameters 5.3. IP Port List 5.4. GTS Reset Sequencer Intel FPGA IP General Interface 5.5. GTS Reset Sequencer Intel FPGA IP Design Flow 5.6. GTS Reset Sequencer Intel FPGA IP Use Cases
5.6. GTS Reset Sequencer Intel FPGA IP Use Cases x
5.6.1. Example Use Case 1 5.6.2. Example Use Case 2
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design x
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP 6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description 6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench 6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design x
6.2.1. Fast Simulation Support 6.2.2. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Directory Structure
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench x
6.4.1. Modifying the Example Design and Performing Simulation
7. Design Assistance Tools x
7.1. Clocking and Datapath Tool 7.2. TX Equalizer Tool
8. Debugging GTS Transceiver Links with Transceiver Toolkit x
8.1. GTS Transceiver Toolkit Parameter Settings 8.2. GTS Transceiver Toolkit GUI 8.3. GTS Transceiver Debugging Flow Walkthrough
8.2. GTS Transceiver Toolkit GUI x
8.2.1. Collection View
8.3. GTS Transceiver Debugging Flow Walkthrough x
8.3.1. Modifying the Design to Enable GTS Transceiver Debug Toolkit 8.3.2. Programming the Design into an Intel FPGA 8.3.3. Loading the Design to the Transceiver Toolkit 8.3.4. Creating Transceiver Links 8.3.5. Running BER Tests 8.3.6. Running Eye Viewer Tests 8.3.7. Running Link Optimization Tests
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide

3.5. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath

The tx_paallel_data bit ad x_paallel_data bit width depeds o the PMA width ad Numbe of PMA laes IP paametes. Use the followig equatio to detemie the total tx_paallel_data o x_paallel_data bit width:

Total tx_paallel_data o x_paallel_data Bit Width Equatio:

tx/x_paallel_data[(80*N)-1:0]

Whee:

  • N = Numbe of PMA laes value fom 1 to 4.

The tx/x_paallel_data sigals iclude the valid paallel data bits ad othe fuctioality bits, such as the data valid bit, the wite eable fo TX coe iteface FIFO i elastic mode bit, the RX deskew bit, ad the aligmet make bits (fo FEC mode). These sigals tavel to ad fom the FPGA fabic to the tasceive block, ad ae clocked by the same paallel clock. This paallel clock ca be a PMA clock o System PLL clock.

Example 1: Total tx/x_paallel_data Bit Width with 2 PMA Laes (N=2) ad 8-bit PMA Width (X=1) 

tx_paallel_data [(80*2)-1:0] = tx_paallel_data [159:0]
x_paallel_data [(80*2)-1:0] = x_paallel_data [159:0]

Paallel Data Mappig ifomatio fo TX ad RX

Table 47.  Vaiable Defiitios
Vaiable Values Desciptio
N 1, 2, 4, 6, 8 Numbe of laes
0 to N-1 N is the PMA idex umbe
D D = PMA Width D is the data width value to calculate the total paallel data bits
Table 48.  PMA Diect Mode Paallel Data Calculatios
PMA Cofiguatio MSB LSB TX Paallel Data RX Paallel Data

PMA Width = 8, 10, 16, 20, 32

Sigle Width

79 Wite Eable fo TX Coe FIFO i Elastic Mode 35 Data valid fo RX Coe FIFO i Elastic Mode35
38 + (80*) TX PMA Iteface Data Valid RX PMA Iteface Data Valid
[D-1] + (80*) 0 + (80*) TX Data RX Data

PMA Width = 8, 10, 16, 20, 32

Double Width

79 Wite Eable fo TX Coe FIFO i Elastic Mode35 Data valid fo RX Coe FIFO i Elastic Mode35
(40+D-1) + (80*) 40 + (80*) TX Data (Uppe Data Bits) RX Data (Uppe Data Bits)
38 + (80*) TX PMA Iteface Data Valid RX PMA Iteface Data Valid
(D -1) + (80*) 0 + (80*) TX Data (Lowe Data Bits) RX Data (Lowe Data Bits)
Table 49.  FEC Diect Mode Paallel Data Calculatios
MSB LSB TX Paallel Data RX Paallel Data
77 Aligmet Make -
72 40 TX Data (Uppe Data Bits) RX Data (Uppe Data Bits)
38 TX PMA Iteface Data Valid Bit RX PMA Iteface Data Valid Bit
37 Aligmet Make Aligmet Make
32 2 TX Data (Lowe Data Bits) RX Data (Lowe Data Bits)
1 0 Syc Head
Table 50.  Example of Bit Mappig of TX Paallel Data Bits fo PMA Diect Mode with PMA Width = 32
N (Numbe of Laes) 1 2 … 4 TX Paallel Data
Bits 79 159 319

Wite Eable fo TX Coe FIFO i Elastic Mode.
38 118 … 278 TX PMA Iteface Data Valid
31:0 118:80 … 271:240 TX Data (Lowe Data Bits)
71:40 151:120 … 311:280 TX Data (Uppe Data Bits)
Table 51.  PCS Diect Mode — IEEE MII Iteface Paallel Data Calculatios
MSB LSB TX Paallel Data RX Paallel Data
74 i_tx_mii_c[7] o_x_mii_c[7]
73 66 i_tx_mii_d[63:56] o_x_mii_d[63:56]
65 i_tx_mii_c[6] o_x_mii_c[6]
64 57 i_tx_mii_d[55:48] o_x_mii_d[55:48]
56 i_tx_mii_c[5] o_x_mii_c[5]
55 48 i_tx_mii_d[47:40] o_x_mii_d[47:40]
47 i_tx_mii_c[4] o_x_mii_c[4]
46 39 i_tx_mii_d[39:32] o_x_mii_d[39:32]
38 i_tx_mii_valid o_x_mii_valid
37 i_tx_mii_am o_x_mii_am
35 i_tx_mii_c[3] o_x_mii_c[3]
34 27 i_tx_mii_d[31:24] o_x_mii_d[31:24]
26 i_tx_mii_c[2] o_x_mii_c[2]
25 18 i_tx_mii_d[23:16] o_x_mii_d[23:16]
17 i_tx_mii_c[1] o_x_mii_c[1]
16 9 i_tx_mii_d[15:8] o_x_mii_d[15:8]
8 i_tx_mii_c[0] o_x_mii_c[0]
7 0 i_tx_mii_d[7:0] o_x_mii_d[7:0]
Table 52.  TX ad RX Paallel Data to IEEE MII Pot Mappig Sigals fo PCS Diect Mode
     
i_tx_mii_d[63:0] Iput Dive MII ecoded cotol bytes o this iput data bus. i_tx_mii_d[7:0] holds the fist byte the IP coe tasmits
i_tx_mii_c[7:0] Iput Fo each cotol byte dive ito i_tx_mii_d bus, dive the coespodig bit high. Fo example, i_tx_mii_c[0] coespods to i_tx_mii_d[7:0]. If the value of a bit is 1, the coespodig data byte is a cotol byte. Othewise it is data.
i_tx_mii_valid Iput Dive this sigal high to qualify the data o cotol bytes o the i_tx_mii_d bus.
i_tx_mii_am Iput Aligmet make isetio bit (applicable oly fo RS-FEC). Dive this sigal to 0 if Fiecode FEC o FEC is ot eabled.
o_x_mii_d[63:0] Output Receive Etheet fames o MII cotol bytes, MII ecoded, o this iput data bus. o_x_mii_d[7:0] holds the fist byte eceived.
o_x_mii_c[15:0] Output Sample this bus to detemie if o_x_mii_d[63:0] iput bus is cayig cotol o data bytes. If the value of a bit is 1, the coespodig data byte is a cotol byte. If the value of a bit is 0, the coespodig data byte is data.
o_x_mii_valid Output Sample this sigal to qualify the RX MII data, RX MII cotol bits, ad the RX valid aligmet make sigals.
Table 53.  PCS Diect Mode — IEEE_FLEXE_66/PCS66 Paallel Data Calculatios
MSB LSB TX Paallel Data RX Paallel Data
71 39 i_txd[65:33] o_xd[65:33]
38 i_tx_valid o_x_valid
37 i_tx_am o_x_am
32 0 i_txd[32:0] o_xd[32:0]
Table 54.  TX ad RX Paallel Data to IEEE_FLEXE_66/PCS66 Mappig Sigals fo PCS Diect Mode
Sigal Name Diectio Desciptio
i_txd[65:0] Iput Dive this data bus with the 66-bit data blocks fom the souce. The two least sigificat bits ae the heade syc bits. I FlexE mode, the TX PCS scambles the 66-bit data block ad stipes the data blocks acoss the tasceive chaels.
i_tx_valid Iput Dive this sigal high to qualify the 66-bit data block o the i_txd iput data bus.
i_tx_am Iput Dive valid 66-bit data blocks whe this sigal has bee asseted. Do ot dive valid data blocks whe this sigal is deasseted.
o_xd[65:0] Output Output data bus that eceives Etheet fames o MII cotol bytes, MII ecoded. o_xd[7:0] holds the fist byte eceived.
o_x_valid Output PCS66 data valid sigal. The sigal idicates valid data o PCS66 pots.
o_x_am Output Aligmet make idicato (applicable fo RS-FEC). This sigal idicates the blocks cuetly o o_xd have bee idetified as aligmet makes.
35 Oly available fo PMA clockig ad if TX/RX coe FIFO is i elastic mode.
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