GTS Transceiver PHY User Guide

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ID 817660
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. GTS Transceiver Overview 2. GTS Transceiver Architecture 3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP 4. Implementing the GTS System PLL Clocks Intel FPGA IP 5. Implementing the GTS Reset Sequencer Intel FPGA IP 6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 7. Design Assistance Tools 8. Debugging GTS Transceiver Links with Transceiver Toolkit 9. Document Revision History for the GTS Transceiver PHY User Guide
1. GTS Transceiver Overview x
1.1. GTS Transceiver Design Flow
2. GTS Transceiver Architecture x
2.1. Building Blocks 2.2. Channel Placement Rules and Design Requirements 2.3. PMA Architecture 2.4. PCS Architecture 2.5. Forward Error Correction (FEC) Architecture 2.6. Clock Architecture 2.7. Bonding and Deskew
2.1. Building Blocks x
2.1.1. PMA 2.1.2. FEC 2.1.3. PCS 2.1.4. Ethernet MAC 2.1.5. PCI Express* Hard IP 2.1.6. PLL and Clock Networks 2.1.7. Avalon® Memory-Mapped Interface
2.1.1. PMA x
2.1.1.1. Protocol Support Using PMA Direct Mode
2.1.1.1. Protocol Support Using PMA Direct Mode x
2.1.1.1.1. SDI 2.1.1.1.2. HDMI 2.1.1.1.3. DisplayPort 2.1.1.1.4. CPRI
2.2. Channel Placement Rules and Design Requirements x
2.2.1. Hard IP Rules 2.2.2. Use Scenario Rules 2.2.3. Unused PMA Rules 2.2.4. General Design Requirement
2.3. PMA Architecture x
2.3.1. Transmitter PMA Architecture 2.3.2. Receiver PMA Architecture 2.3.3. PMA Loopback Modes
2.3.1. Transmitter PMA Architecture x
2.3.1.1. Transmitter Buffer 2.3.1.2. Serializer 2.3.1.3. Data Pattern Generator and Verifier
2.3.2. Receiver PMA Architecture x
2.3.2.1. Receiver Buffer and Equalizer 2.3.2.2. Deserializer 2.3.2.3. CDR Block 2.3.2.4. PMA Tuning
2.3.2.1. Receiver Buffer and Equalizer x
2.3.2.1.1. Control Unit
2.5. Forward Error Correction (FEC) Architecture x
2.5.1. FEC Loopback Mode
2.6. Clock Architecture x
2.6.1. Reference Clock Network 2.6.2. Datapath Clock Network 2.6.3. System PLL 2.6.4. Datapath Clock Cadences 2.6.5. Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank
2.6.1. Reference Clock Network x
2.6.1.1. Single GTS Transceiver Bank Device 2.6.1.2. PMA Primary PLL Configuration
2.6.3. System PLL x
2.6.3.1. I/O PLLs in HVIO Bank as System PLL 2.6.3.2. Running PCIe* and Non- PCIe* Protocols in a GTS Transceiver Bank 2.6.3.3. System PLL Clock for FPGA Core 2.6.3.4. System PLL with HVIO Reference Clock
2.7. Bonding and Deskew x
2.7.1. Bonding Architecture 2.7.2. TX Deskew Function
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.1. IP Overview 3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP 3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting reset 3.9. Bonding Implementation 3.10. Configuration Register 3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing 3.12. Configurable Quartus® Prime Software Settings 3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. PCS Direct Supported Modes 3.1.4. Unsupported PMA/FEC/PCS Modes
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.3.1. Preset IP Parameter Settings 3.3.2. Common Datapath Options 3.3.3. TX Datapath Options 3.3.4. RX Datapath Options 3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations 3.3.6. FEC Options 3.3.7. PCS Options 3.3.8. Avalon® Memory-Mapped Interface Options 3.3.9. Register Map IP-XACT Support 3.3.10. Analog Parameter Options
3.3.3. TX Datapath Options x
3.3.3.1. TX PMA Interface Parameters
3.3.4. RX Datapath Options x
3.3.4.1. RX PMA Interface Parameters
3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations x
3.3.5.1. PMA Configuration Rules for SDI Mode 3.3.5.2. PMA Configuration Rules for HDMI Mode 3.3.5.3. PMA Configuration Rules for DisplayPort Mode 3.3.5.4. PMA Configuration Rules for CPRI Mode
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. RX PMA Status Signals 3.4.7. TX and RX PMA and Core Interface FIFO Signals 3.4.8. Avalon Memory-Mapped Interface Signals
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. PMA Fractional Mode
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the i_tx_cadence_slow_clk_locked Port
3.8. Asserting reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Run-time Reset Sequence—TX 3.8.5. Run-time Reset Sequence—RX 3.8.6. Run-time Reset Sequence—TX + RX 3.8.7. RX Data Loss/CDR Lock Loss (Auto-Recovery) 3.8.8. TX PLL Lock Loss
3.9. Bonding Implementation x
3.9.1. Bonding Placement Requirements
3.10. Configuration Register x
3.10.1. GTS PMA and FEC Direct PHY Soft CSR Register Map 3.10.2. GTS PMA Register Map 3.10.3. Accessing Configuration Registers
3.10.2. GTS PMA Register Map x
3.10.2.1. Logical Avalon® Memory-Mapped Port Indexing
3.10.3. Accessing Configuration Registers x
3.10.3.1. Accessing GTS PMA and FEC Direct PHY Soft CSR Registers 3.10.3.2. Accessing GTS PMA Registers
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing x
3.11.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP 3.11.2. Using JTAG to Avalon Master Bridge Intel FPGA IP
3.11.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.11.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.11.2. Using JTAG to Avalon Master Bridge Intel FPGA IP x
3.11.2.1. RTL Connection Example for JTAG to Avalon Master Bridge Intel® FPGA IP
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.13.1. Direct Register Method 3.13.2. GTS Attribute Access Method
3.13.1. Direct Register Method x
3.13.1.1. Direct Register Method Examples
3.13.2. GTS Attribute Access Method x
3.13.2.1. GTS Attribute Access Method Example 1 3.13.2.2. GTS Attribute Access Method Example 2
4. Implementing the GTS System PLL Clocks Intel FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for GTS System PLL Clocks Intel FPGA IP Usage 4.5. Guidelines to Indicate System PLL Reference Clock is Ready
4.5. Guidelines to Indicate System PLL Reference Clock is Ready x
4.5.1. Example Flow to Indicate System PLL Reference Clock is Ready
5. Implementing the GTS Reset Sequencer Intel FPGA IP x
5.1. IP Requirements 5.2. IP Parameters 5.3. IP Port List 5.4. GTS Reset Sequencer Intel FPGA IP General Interface 5.5. GTS Reset Sequencer Intel FPGA IP Design Flow 5.6. GTS Reset Sequencer Intel FPGA IP Use Cases
5.6. GTS Reset Sequencer Intel FPGA IP Use Cases x
5.6.1. Example Use Case 1 5.6.2. Example Use Case 2
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design x
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP 6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description 6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench 6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design x
6.2.1. Fast Simulation Support 6.2.2. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Directory Structure
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench x
6.4.1. Modifying the Example Design and Performing Simulation
7. Design Assistance Tools x
7.1. Clocking and Datapath Tool 7.2. TX Equalizer Tool
8. Debugging GTS Transceiver Links with Transceiver Toolkit x
8.1. GTS Transceiver Toolkit Parameter Settings 8.2. GTS Transceiver Toolkit GUI 8.3. GTS Transceiver Debugging Flow Walkthrough
8.2. GTS Transceiver Toolkit GUI x
8.2.1. Collection View
8.3. GTS Transceiver Debugging Flow Walkthrough x
8.3.1. Modifying the Design to Enable GTS Transceiver Debug Toolkit 8.3.2. Programming the Design into an Intel FPGA 8.3.3. Loading the Design to the Transceiver Toolkit 8.3.4. Creating Transceiver Links 8.3.5. Running BER Tests 8.3.6. Running Eye Viewer Tests 8.3.7. Running Link Optimization Tests
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide

6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design

To geeate the example desig you eed to ope the GTS PMA/FEC Diect PHY Itel FPGA IP ad go to the Example Desig tab. The GTS PMA/FEC Diect PHY Itel FPGA IP paamete edito icludes the Geeate Example Desig fuctio to easily ceate ad geeate simulatio files to simulate a GTS PMA o FEC diect mode example desig.

You ca cuetly select ay oe of the Example Desig Optios fo geeatio as show i the followig table.
Table 82.  Example Desig Optios
Example Desig Optios Desciptio
1 x 10.3125G FEC Diect Mode (System PLL Clockig) Oe NRZ Fiecode FEC Diect GTS lae, with a thoughput of 10.3125 Gbps, with System PLL clockig mode
1 x 10.3125G Fiecode FEC PCS Mode (System PLL Clockig) Oe NRZ Fiecode FEC ad PCS Diect GTS lae, with a thoughput of 10.3125 Gbps, with System PLL clockig mode
1 x 10.3125G RSFEC Diect Mode (System PLL Clockig) Oe NRZ RS-FEC FEC Diect GTS lae, with a thoughput of 10.3125 Gbps, with System PLL clockig mode
1 x 17.16G RSFEC Diect Mode (System PLL Clockig) Oe NRZ RS-FEC FEC Diect GTS lae, with a thoughput of 17.160 Gbps, with System PLL clockig mode
1 x 17.16G PCS Diect Mode (System PLL Clockig) Oe NRZ PCS Diect GTS lae, with a thoughput of 17.160 Gbps, with System PLL clockig mode
1 x 10.3125G PMA Diect Mode (System PLL Clockig) with Custom Cadece

Oe NRZ PMA Diect GTS lae, with a thoughput of 10.3125 Gbps, with System PLL clockig mode ad custom cadecig
4 x 10.3125G PMA Diect Mode (PMA Clockig)

Fou NRZ PMA Diect GTS lae, with 10.3125 Gbps pe PMA lae, with PMA clockig mode
1 x 1G PMA Diect Mode (System PLL Clockig) with Custom Cadece

Oe NRZ PMA Diect GTS lae, with a thoughput of 1Gbps, with System PLL clockig mode ad custom cadecig
1 x 3.125G PMA Diect Mode (System PLL Clockig) with Custom Cadece

Oe NRZ PMA Diect GTS lae, with a thoughput of 3.125 Gbps, with System PLL clockig mode ad custom cadecig.
1 x 28.1G Fie code FEC Diect Mode (System PLL Clockig) Oe NRZ Fiecode FEC Diect GTS lae, with a thoughput of 28.1 Gbps, with System PLL clockig mode.
1 x 28.1G RSFEC Diect Mode (System PLL Clockig) Oe NRZ RS-FEC FEC Diect GTS lae, with a thoughput of 28.1 Gbps, with System PLL clockig mode.
1 x 28.1G PMA Diect Mode (System PLL Clockig) Oe NRZ PMA Diect GTS lae, with a thoughput of 28.1 Gbps, with System PLL clockig mode.
1 x 28.1G PMA Diect Mode (PMA Clockig) Oe NRZ PMA Diect GTS lae, with a thoughput of 28.1 Gbps, with PMA clockig mode.
To geeate a example desig, follow the steps below:
  1. Go to the Example Desig tab i the GTS PMA/FEC Diect PHY Itel FPGA IP.
  2. Select oe of the example desigs fom the dop-dow meu. If you select Noe you caot geeate the example desig.
  3. Click the Ackowledgmet optio box. This optio is to emid you that oly the example desig you specify i the dop-dow meu is geeated. If you make ay modificatio to the paamete settigs of the IP afte selectig the Example Desig optios fom the dop dow list, the chages you make to the IP paametes do ot take effect. Oly the paametes defied fo the Example Desig optios i Example Desig Optios table take effect. If you do ot check the ackowledgmet box, you caot geeate the example desig.
  4. If you ae usig Agilex™ 5 FPGA pemium developmet kit, you ca select the boad Itel Agilex™ 5 FPGA E-Seies 065B Pemium Developmet Kit (ES1) i the dop-dow list. With this selectio, the Quatus® Pime Po Editio softwae geeates the example desig with the efeece clock ad chael pi assigmets i the .qsf file.
  5. Esue steps 2. ad step 3. ae doe, the click Geeate Example Desig. Clickig Geeate Example Desig completes the IP Geeatio. A example desig folde is geeated cotaiig the Quatus® Pime softwae poject (.qpf), settigs (.qsf), ad IP files. I additio, thee ae two foldes ceated amed tl ad testbech cotaiig the RTL ad simulatio testbech files i the followig locatio: 
    <Poject Folde>/<diectphy_example_desig/example_desig>
Figue 83. GTS PMA/FEC Diect PHY Itel FPGA IP Example Desig Steps
Figue 84. GTS PMA/FEC Diect PHY Itel FPGA IP Example Desig Boad Selectio
Note: If you select ay of the seve available Example Desig Optios, but chage the GTS PMA/FEC Diect PHY Itel FPGA IP settigs i the GUI theeafte, the example desig geeated does ot follow the chaged settigs fo the GTS PMA/FEC Diect PHY Itel FPGA IP. The example desig geeatio oly takes the Example Desig Optios listed i Example Desig tab of the IP Paamete edito. Ay othe chages that you make to the GTS PMA/FEC Diect PHY Itel FPGA IP settigs ae ot applied duig example desig geeatio.
Note: Fo the Select Boad optio i the Example Desig tab of the IP Paamete edito, oly the Itel Agilex™ 5 FPGA E-Seies 065B Pemium Developmet Kit (ES1) optio appeas i the dop-dow list, eve if you select a Agilex™ 5 D-Seies ad E-Seies Device Goup A FPGAs i the Quatus® Pime Po Editio softwae.
Note: Whe you geeate the GTS PMA/FEC Diect PHY Itel FPGA IP example desigs, the JTAG to Avalo Maste Bidge Itel FPGA IP istace is used to coect to the Avalo® memoy-mapped iteface. If you wat to use the Debug Edpoit iteface to coect to the Avalo® memoy-mapped iteface, you must eable the fuctioality ude the Avalo® Memoy-Mapped Iteface tab of the IP GUI. I additio, you must chage the ecofiguatio iteface coectios of the IP by followig the istuctios i Usig Debug Edpoit Iteface withi the GTS PMA/FEC Diect PHY Itel FPGA IP.

Sectio Cotet
Fast Simulatio Suppot
GTS PMA/FEC Diect PHY Itel FPGA IP Example Desig Diectoy Stuctue

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