GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP

The GTS PMA/FEC Direct PHY Intel FPGA IP is the primary IP component for PMA, FEC, and PCS direct usage. This IP provides direct access to the Agilex™ 5 GTS PMA block features.

To customize and instantiate the IP for your protocol implementation, you specify parameter values for the GTS PMA/FEC Direct PHY Intel FPGA IP and generate the IP RTL and supporting files from the Quartus® Prime parameter editor. The top-level file generated with the IP instance includes all the available ports for your configuration.

The GTS PMA/FEC Direct PHY Intel FPGA IP allows you to configure and support PMA, FEC, and PCS direct modes with the following:
  • Datapath Clocking mode, PMA mode, PMA data rate, PMA width
  • TX datapath and RX datapath options settings (FIFO modes, TX PLL, RX CDR)
  • FEC options such as FEC mode selection and FEC loopback mode
  • PCS options such as PCS mode selection
  • Avalon® Memory-Mapped Interface
The following figure shows the block diagram of the GTS PMA/FEC Direct PHY Intel FPGA IP connections to the relevant IP blocks. This is an example of the connections that you have to make for the system PLL clocking mode. If you are using the PMA clocking mode, you do not need to instantiate the GTS System PLL Clocks Intel FPGA IP.
Figure 38. GTS PMA/FEC Direct PHY Intel FPGA IP Connections