GTS Transceiver PHY User Guide

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ID 817660
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. GTS Transceiver Overview 2. GTS Transceiver Architecture 3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP 4. Implementing the GTS System PLL Clocks Intel FPGA IP 5. Implementing the GTS Reset Sequencer Intel FPGA IP 6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 7. Design Assistance Tools 8. Debugging GTS Transceiver Links with Transceiver Toolkit 9. Document Revision History for the GTS Transceiver PHY User Guide
1. GTS Transceiver Overview x
1.1. GTS Transceiver Design Flow
2. GTS Transceiver Architecture x
2.1. Building Blocks 2.2. Channel Placement Rules and Design Requirements 2.3. PMA Architecture 2.4. PCS Architecture 2.5. Forward Error Correction (FEC) Architecture 2.6. Clock Architecture 2.7. Bonding and Deskew
2.1. Building Blocks x
2.1.1. PMA 2.1.2. FEC 2.1.3. PCS 2.1.4. Ethernet MAC 2.1.5. PCI Express* Hard IP 2.1.6. PLL and Clock Networks 2.1.7. Avalon® Memory-Mapped Interface
2.1.1. PMA x
2.1.1.1. Protocol Support Using PMA Direct Mode
2.1.1.1. Protocol Support Using PMA Direct Mode x
2.1.1.1.1. SDI 2.1.1.1.2. HDMI 2.1.1.1.3. DisplayPort 2.1.1.1.4. CPRI
2.2. Channel Placement Rules and Design Requirements x
2.2.1. Hard IP Rules 2.2.2. Use Scenario Rules 2.2.3. Unused PMA Rules 2.2.4. General Design Requirement
2.3. PMA Architecture x
2.3.1. Transmitter PMA Architecture 2.3.2. Receiver PMA Architecture 2.3.3. PMA Loopback Modes
2.3.1. Transmitter PMA Architecture x
2.3.1.1. Transmitter Buffer 2.3.1.2. Serializer 2.3.1.3. Data Pattern Generator and Verifier
2.3.2. Receiver PMA Architecture x
2.3.2.1. Receiver Buffer and Equalizer 2.3.2.2. Deserializer 2.3.2.3. CDR Block 2.3.2.4. PMA Tuning
2.3.2.1. Receiver Buffer and Equalizer x
2.3.2.1.1. Control Unit
2.5. Forward Error Correction (FEC) Architecture x
2.5.1. FEC Loopback Mode
2.6. Clock Architecture x
2.6.1. Reference Clock Network 2.6.2. Datapath Clock Network 2.6.3. System PLL 2.6.4. Datapath Clock Cadences 2.6.5. Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank
2.6.1. Reference Clock Network x
2.6.1.1. Single GTS Transceiver Bank Device 2.6.1.2. PMA Primary PLL Configuration
2.6.3. System PLL x
2.6.3.1. I/O PLLs in HVIO Bank as System PLL 2.6.3.2. Running PCIe* and Non- PCIe* Protocols in a GTS Transceiver Bank 2.6.3.3. System PLL Clock for FPGA Core 2.6.3.4. System PLL with HVIO Reference Clock
2.7. Bonding and Deskew x
2.7.1. Bonding Architecture 2.7.2. TX Deskew Function
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.1. IP Overview 3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP 3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting reset 3.9. Bonding Implementation 3.10. Configuration Register 3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing 3.12. Configurable Quartus® Prime Software Settings 3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. PCS Direct Supported Modes 3.1.4. Unsupported PMA/FEC/PCS Modes
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.3.1. Preset IP Parameter Settings 3.3.2. Common Datapath Options 3.3.3. TX Datapath Options 3.3.4. RX Datapath Options 3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations 3.3.6. FEC Options 3.3.7. PCS Options 3.3.8. Avalon® Memory-Mapped Interface Options 3.3.9. Register Map IP-XACT Support 3.3.10. Analog Parameter Options
3.3.3. TX Datapath Options x
3.3.3.1. TX PMA Interface Parameters
3.3.4. RX Datapath Options x
3.3.4.1. RX PMA Interface Parameters
3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations x
3.3.5.1. PMA Configuration Rules for SDI Mode 3.3.5.2. PMA Configuration Rules for HDMI Mode 3.3.5.3. PMA Configuration Rules for DisplayPort Mode 3.3.5.4. PMA Configuration Rules for CPRI Mode
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. RX PMA Status Signals 3.4.7. TX and RX PMA and Core Interface FIFO Signals 3.4.8. Avalon Memory-Mapped Interface Signals
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. PMA Fractional Mode
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the i_tx_cadence_slow_clk_locked Port
3.8. Asserting reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Run-time Reset Sequence—TX 3.8.5. Run-time Reset Sequence—RX 3.8.6. Run-time Reset Sequence—TX + RX 3.8.7. RX Data Loss/CDR Lock Loss (Auto-Recovery) 3.8.8. TX PLL Lock Loss
3.9. Bonding Implementation x
3.9.1. Bonding Placement Requirements
3.10. Configuration Register x
3.10.1. GTS PMA and FEC Direct PHY Soft CSR Register Map 3.10.2. GTS PMA Register Map 3.10.3. Accessing Configuration Registers
3.10.2. GTS PMA Register Map x
3.10.2.1. Logical Avalon® Memory-Mapped Port Indexing
3.10.3. Accessing Configuration Registers x
3.10.3.1. Accessing GTS PMA and FEC Direct PHY Soft CSR Registers 3.10.3.2. Accessing GTS PMA Registers
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing x
3.11.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP 3.11.2. Using JTAG to Avalon Master Bridge Intel FPGA IP
3.11.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.11.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.11.2. Using JTAG to Avalon Master Bridge Intel FPGA IP x
3.11.2.1. RTL Connection Example for JTAG to Avalon Master Bridge Intel® FPGA IP
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.13.1. Direct Register Method 3.13.2. GTS Attribute Access Method
3.13.1. Direct Register Method x
3.13.1.1. Direct Register Method Examples
3.13.2. GTS Attribute Access Method x
3.13.2.1. GTS Attribute Access Method Example 1 3.13.2.2. GTS Attribute Access Method Example 2
4. Implementing the GTS System PLL Clocks Intel FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for GTS System PLL Clocks Intel FPGA IP Usage 4.5. Guidelines to Indicate System PLL Reference Clock is Ready
4.5. Guidelines to Indicate System PLL Reference Clock is Ready x
4.5.1. Example Flow to Indicate System PLL Reference Clock is Ready
5. Implementing the GTS Reset Sequencer Intel FPGA IP x
5.1. IP Requirements 5.2. IP Parameters 5.3. IP Port List 5.4. GTS Reset Sequencer Intel FPGA IP General Interface 5.5. GTS Reset Sequencer Intel FPGA IP Design Flow 5.6. GTS Reset Sequencer Intel FPGA IP Use Cases
5.6. GTS Reset Sequencer Intel FPGA IP Use Cases x
5.6.1. Example Use Case 1 5.6.2. Example Use Case 2
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design x
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP 6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description 6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench 6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design x
6.2.1. Fast Simulation Support 6.2.2. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Directory Structure
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench x
6.4.1. Modifying the Example Design and Performing Simulation
7. Design Assistance Tools x
7.1. Clocking and Datapath Tool 7.2. TX Equalizer Tool
8. Debugging GTS Transceiver Links with Transceiver Toolkit x
8.1. GTS Transceiver Toolkit Parameter Settings 8.2. GTS Transceiver Toolkit GUI 8.3. GTS Transceiver Debugging Flow Walkthrough
8.2. GTS Transceiver Toolkit GUI x
8.2.1. Collection View
8.3. GTS Transceiver Debugging Flow Walkthrough x
8.3.1. Modifying the Design to Enable GTS Transceiver Debug Toolkit 8.3.2. Programming the Design into an Intel FPGA 8.3.3. Loading the Design to the Transceiver Toolkit 8.3.4. Creating Transceiver Links 8.3.5. Running BER Tests 8.3.6. Running Eye Viewer Tests 8.3.7. Running Link Optimization Tests
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide

3.12. Configurable Quartus® Prime Software Settings

You ca cofigue the GTS PMAs usig the Quatus® Pime softwae settigs (.qsf) file. You ca also cofigue the HSSI TX ad RX paametes though the Aalog Paamete Optios i the IP GUI. Howeve, cofiguig the HSSI aalog paametes though the .qsf file takes pecedece ove the IP GUI settigs.

You ca specify values fo the followig HSSI paametes i the Quatus® Pime settigs file (.qsf) o use the Assigmet Edito of the Quatus® Pime Po Editio softwae to cofigue the GTS PMAs:

TX Equalizatio: 

set_istace_assigmet -ame HSSI_PARAMETER "tx_eq_mai_tap=<paamete_value>" -to <TX_SERIAL_PIN> -etity <TOP_LEVEL_NAME>
Valid paamete settigs:
  • Mai_tap: 0-55
  • Pe_tap_1: 0-15
  • Pe_tap_2: 0-7
  • Post_tap_1: 0-19
Table 67.  TX Equalizatio HSSI Paamete Name ad Values
HSSI Paamete Name Valid Paamete Values (Decimal)
tx_eq_mai_tap 0-55
tx_eq_pe_tap_1 0-15
tx_eq_pe_tap_2 0-7
tx_eq_post_tap_1 0-19
Note: Refe to the TX Equalize tool fo the legal combiatios.
Example assigmets i .qsf file: 
  • set_istace_assigmet -ame HSSI_PARAMETER "tx_eq_mai_tap=41" -to c12tx_seial[0] -etity top
  • set_istace_assigmet -ame HSSI_PARAMETER "tx_eq_pe_tap_1=1" -to c12tx_seial[0] -etity top
  • set_istace_assigmet -ame HSSI_PARAMETER "tx_eq_pe_tap_2=0" -to c12tx_seial[0] -etity top
  • set_istace_assigmet -ame HSSI_PARAMETER "tx_eq_post_tap_1=4" -to c12tx_seial[0] -etity top
Figue 70. Assigmet Edito Example fo TX Equalizatio
Note: It is ecommeded that you set some baselie values fo the TX equalizatio paametes fo you desig to optimize the GTS PMA tasmitte. You ca use the GTS Tasceive Toolkit Paamete Settigs to tue ad fid the optimal settigs fo you lik.

RX AC Couplig: 

set_istace_assigmet -ame HSSI_PARAMETER "x_exteal_couple_type=<paamete_value>" -to <RX_SERIAL_PIN> -etity <TOP_LEVEL_NAME>
You must set the coect RX AC couplig type accodig to you RX exteal couplig lik setup. The valid paamete settigs:

  • RX_EXTERNAL_COUPLE_TYPE_AC: Whe you use exteal AC couplig capacitos i you lik.

  • RX_EXTERNAL_COUPLE_TYPE_DC: Whe you do ot use exteal AC couplig capacitos i you lik.

Table 68.  RX AC Couplig HSSI Paamete Name ad Values
HSSI Paamete Name Valid Paamete Values Use Case
x_exteal_couple_type RX_EXTERNAL_COUPLE_TYPE_AC Whe AC couplig capacito is used exteally i the lik.
x_exteal_couple_type RX_EXTERNAL_COUPLE_TYPE_DC Whe AC couplig capacito is ot used exteally i the lik.
Example assigmet i .qsf file: 
set_istace_assigmet -ame HSSI_PARAMETER "x_exteal_couple_type=RX_EXTERNAL_COUPLE_TYPE_AC" -to c12x_seial[0] -etity top
Figue 71. Assigmet Edito Example fo RX AC Couplig

RX Temiatio Mode: 

set_istace_assigmet -ame HSSI_PARAMETER "x_temiatio_mode=<paamete_value> -to <RX_SERIAL_PIN> -etity
<TOP_LEVEL_NAME>
Valid paamete settigs:

  • RX_TERMINATION_MODE_GROUNDED: Gouded temiatio mode fo AC coupled lik

  • RX_TERMINATION_MODE_DIFFERENTIAL: Diffeetial temiatio mode fo DC coupled lik39

Table 69.  RX Temiatio Mode HSSI Paamete Name ad Values
HSSI Paamete Name Valid Paamete Values Use Case
x_temiatio_mode RX_TERMINATION_MODE_GROUNDED Fo AC coupled lik (whe you eable AC couplig exteally)
x_temiatio_mode RX_TERMINATION_MODE_DIFFERENTIAL Fo DC coupled lik (whe you do ot eable AC couplig exteally)
Example assigmet i .qsf file: 
set_istace_assigmet -ame HSSI_PARAMETER "x_temiatio_mode=RX_TERMINATION_MODE_GROUNDED" -to c12x_seial[0]” -etity top
set_istace_assigmet -ame HSSI_PARAMETER "x_temiatio_mode=RX_TERMINATION_MODE_DIFFERENTIAL" -to c12x_seial[0]” -etity top
Note: The x_temiatio_mode is cuetly set by default to the GROUNDED mode i the GTS PMA/FEC Diect PHY Itel FPGA IP.

RX O-Chip Temiatio: 

set_istace_assigmet -ame HSSI_PARAMETER "x_ochip_temiatio_settig=<paamete_value>" -to <RX_SERIAL_PIN> -etity <TOP_LEVEL_NAME>
Valid paamete settigs:

  • RX_ONCHIP_TERMINATION_SETTING_R_1: 85 Ohms

  • RX_ONCHIP_TERMINATION_SETTING_R_2: 100 Ohms

Table 70.  RX O-Chip Temiatio HSSI Paamete Name ad Values
HSSI Paamete Name Valid Paamete Values Use Case
x_ochip_temiatio_settig RX_ONCHIP_TERMINATION_SETTING_R_1 85 Ohm
x_ochip_temiatio_settig RX_ONCHIP_TERMINATION_SETTING_R_2 100 Ohm
Example assigmet i .qsf file: 
set_istace_assigmet -ame HSSI_PARAMETER "x_ochip_temiatio_settig=RX_ONCHIP_TERMINATION_SETTING_R_2" -to  c12x_seial[0] -etity top
Figue 72. Assigmet Edito Example fo RX O-Chip Temiatio
Note: It is ecommeded that you set the x_ochip_temiatio_settig paamete based o you tasmissio lik chaacteistic impedace.

RX Maual Tuig:

If you cofigue the RX lik to maual tuig mode (RX adaptatio mode is set to maual mode i the IP GUI), you must povide the RX PMA aalog settigs. You ca use the GTS Tasceive Toolkit Paamete Settigs to tue the lik duig maual adaptatio mode to fid the optimal settig fo the RX aalog paametes. You ca cotol the VGA gai, High fequecy boost, ad DFE Tap 1 PMA settigs by selectig the value i the Aalog Paametes tab o by usig the followig .qsf settigs show below:

  • VGA gai:
    set_istace_assigmet -ame HSSI_PARAMETER "x_eq_vga_gai=<paamete_value>" -to <RX_SERIAL_PIN> -etity <TOP_LEVEL_NAME>
    Valid paamete values (decimal) ae 0-63.
  • High fequecy boost:
    set_istace_assigmet -ame HSSI_PARAMETER "x_eq_hf_boost=<paamete_value>" -to <RX_SERIAL_PIN> -etity <TOP_LEVEL_NAME>
    Valid paamete values (decimal) ae 0-63.
  • DFE Tap 1:
    set_istace_assigmet -ame HSSI_PARAMETER "x_eq_dfe_tap_1=<paamete_value>" -to <RX_SERIAL_PIN> -etity <TOP_LEVEL_NAME>
    Valid paamete values (decimal) ae 0-63.
    Note: If you ae usig the auto adaptatio mode, do ot cofigue the VGA gai, High fequecy boost, ad DFE Tap 1 PMA settigs i the .qsf file, as it esults i a compilatio eo.
39 Pelimiay settig pedig hadwae veificatio.
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