Visible to Intel only — GUID: bmj1682963538496
Ixiasoft
Visible to Intel only — GUID: bmj1682963538496
Ixiasoft
3.10.2.1. Logical Avalon® Memory-Mapped Port Indexing
This section explains how to access the GTS PMA lanes if your design has more than one GTS PMA lane. You need to know how to control the logical Avalon® memory-mapped port indexing if you are using the shared reconfiguration interface. (Enable separate Avalon interface per PMA = Off).
If your design has the Enable separate Avalon interface per PMA = On feature enabled, each Avalon® memory-mapped interface has its own reconfiguration interface and you can directly access the port’s register address without following the logical port indexing instruction explained in this section.
- 18 bits for the PMA Avalon memory-mapped reconfiguration interface (i_reconfig_address[17:0])
The reconfiguration address space grows as a function of the following equation:
log2(N)(where N = number of lanes), for an increase in the number of PMA lanes. The additional MSB bits of the reconfiguration address bus represent the logical Avalon® memory-mapped port index value. Refer to MSB Address Bits for PMA Logical Avalon® Memory-Mapped Reconfiguration Port Index Value for more information.
For example, if you enable four PMA lanes in your design, for the Avalon® memory-mapped interface, the total reconfiguration address bus is i_reconfig_address[19:0]. The Avalon® memory-mapped interfaces MSB address bits (i_reconfig_address[19:18]) provide the logical mapping to access different lanes based on the number of PMA lanes. The two additional MSB address bits (i_reconfig_address[19:18]) are a logical representation of the Avalon® memory-mapped interface port. You can use them to read or write to the individual Avalon® memory-mapped interface defined within the IP.
The following table shows the MSB address bits for logical Avalon® memory-mapped port indexing with the number of PMA lanes configured in the IP.
PMA Lane Set in GUI | Reconfiguration Address Bus 40 | MSB Address Bits for Logical Avalon® Memory-Mapped Port Indexing | Logical Avalon® Memory-Mapped Port Indexing (value=hex) |
---|---|---|---|
1 | i_reconfig_address[17:0] | Not Applicable | 0 |
2 | i_reconfig_address[18:0] | [18] | 0,1 |
4 | i_reconfig_address[19:0] | [19:18] | 0,1,2,3 |
6, 8 | i_reconfig_address[20:0] | [20:18] | 0,1,2,3,4,5,6,7 |
Example 1: Performing a Read Operation for TX EQ pre_tap_1 Register (0x091750[9:5]) in Simulation
- For lane 0: 0x091750 ÷ 4 = 0x245D4
- For lane 1: 0x191750 ÷ 4 = 0x645D4
avmm_read(21'h245D4,rdata,32'habcd_ef01,1); // To read TX EQ pre_tap_1 for lane 0 repeat (5) @(posedge mgmt_clk); avmm_read(21'h645D4,rdata,32'habcd_ef01,1); // To read TX EQ pre_tap_1 for lane 1 repeat (5) @(posedge mgmt_clk);