GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

6.2.1. Fast Simulation Support

The design example testbench uses a Fast Sim model to reduce the simulation time duration. You can enable the model via a macro in the simulation run scripts. To enable the Fast Sim model, use the following syntax:
+define+IP7521SERDES_UX_SIMSPEED

This macro is enabled by default in the example design simulation scripts after you click Generate Example Design button.

You can use the Fast Sim model when you are simulating the GTS PMA/FEC Direct PHY Intel FPGA IP design to reduce simulation time. However, you must ensure all the IPs in your design support Fast Sim mode. For example; if you have a PMA direct mode design together with other protocol IPs that do not support the Fast Sim mode, you may run into simulation errors for your PMA direct design.
Note: This macro is not available when you use TX PLL cascade mode and dual-simplex mode.