GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

6.2.2. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Directory Structure

The example design RTL files are in the example_design/rtl directory and simulation files are in the example_design/testbench directory. The GTS PMA/FEC Direct PHY Intel FPGA IP example design generates the following files:
Table 78.  Example Design Directory Structure and Description
Directory Structure and File Name Description
Key testbench and simulation files for the GTS PMA/FEC Direct PHY Intel FPGA IP Example Designs
<directphy_example_design>/example_design/rtl/top_tst.sv Top-level testbench file. The testbench instantiates the top.v PMA direct design file.
<directphy_example_design>/example_design/rtl/testwrap_pma_direct.sv Test wrapper file that generates and receives the PRBS data stream as well as performs the TX and RX clock output frequency checks.
Testbench scripts for the GTS PMA/FEC Direct PHY Intel FPGA IP Example Designs
<directphy_example_design>/example_design/testbench/run_vcsmx.sh The VCS* MX script to run the testbench.
<directphy_example_design>/example_design/testbench/run_xcelium.sh The Xcelium* script to run the testbench.
<directphy_example_design>/example_design/testbench/run_vsim.tcl The QuestaSim* script to run the testbench.