GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.3.4. RX Datapath Options

Figure 43. RX Datapath Options in Parameter Editor
Table 25.  RX Datapath Options Parameters
Parameter Values Description

Enable rx_cdr_divclk

On/Off

Enables the port representing RX CDR clock output from RX PMA to the local reference clock pin (set as output) or the CDR clock output pin. The physical port is typically used for CPRI. Default value is Off.

RX CDR Settings
Output frequency Output Specifies the non editable RX CDR output frequency initial value derived from the IP configuration.
VCO frequency Output Specifies the non editable RX CDR VCO frequency initial value derived from the IP configuration.
RX CDR reference clock frequency 25 to 380 MHz Selects the reference clock frequency (MHz) for CDR. Default value is 156.25 MHz.
CDR lock mode auto

manual

When auto is selected, during user initiated reset or power-up, CDR first tries to lock to reference and then locks to data if present. By default, loss of lock to data re-triggers reset RX PMA reset. When manual is selected, you must drive i_rx_set_locktoref to control the CDR lock behavior. If i_rx_set_locktoref is low CDR operates in auto mode, and in lock to reference mode if it is high. When Enable rx_cdr_divclk is enabled, only auto mode is available. Default value is auto.
Enable rx_set_locktoref port On/Off This parameter is valid only when CDR lock mode is set to manual lock to reference. Asserting this signal keeps CDR in lock to reference mode. Deasserting this signal keeps CDR in auto mode. When switching modes, assert reset. Default value is Off