GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

2.1.3. PCS

Each PMA channel supports connecting to an IEEE 802.3 compliant Clause 49 or Clause 107 PCS layer with 64b/66b encoding and decoding, data scrambling, block alignment and gearbox functions. The PCS block enables Ethernet 10G/25G, CPRI (64b/66b encoded), and OTN implementations .
The PCS function is supported using the GTS PMA/FEC Direct PHY Intel FPGA IP and the GTS Ethernet Intel FPGA Hard IP. Refer to Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP and the GTS Ethernet Intel FPGA Hard IP User Guide for Agilex™ 5 devices for details.