Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 4/01/2024
Public
Document Table of Contents

5.13.3. UART Controller Features

The UART controller provides the following functionality and features:

  • Programmable character properties, such as number of data bits per character, optional parity bits, and number of stop bits
  • Line break generation and detection
  • DMA controller handshaking interface
  • Prioritized interrupt identification
  • Programmable baud rate
  • False start bit detection
  • Automatic flow control mode per 16750 standard
  • Internal loopback mode support
  • 128-byte transmit and receive FIFO buffers
    • FIFO buffer status registers
    • FIFO buffer access mode (for FIFO buffer testing) enables write of receive FIFO buffer by master and read of transmit FIFO buffer by master
  • Shadow registers reduce software overhead and provide programmable reset
  • Transmitter holding register empty (THRE) interrupt mode
  • Separate thresholds for DMA request and handshake signals to maximize throughput