Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

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ID 814346
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Hard Processor System Technical Reference Manual Revision History 2. Introduction to the Hard Processor System 3. Micro Processor Unit (MPU) 4. Application Processor Subsystem 5. Peripheral Subsystem 6. System Manager 7. Clock Manager 8. Reset Manager 9. Power Management 10. Address Map 11. Bridges 12. Interfaces 13. System Interconnect and Firewalls 14. Error Checking and Correction Controller 15. CoreSight Debug and Trace 16. HPS Register Map A. Appendix
1. Agilex™ 5 Hard Processor System Technical Reference Manual Revision History x
1.1. Introduction to the HPS Revision History 1.2. MPU Revision History 1.3. CCU Revision History 1.4. GIC Revision History 1.5. SMMU Revision History 1.6. On-Chip RAM Revision History 1.7. EMAC Revision History 1.8. DMA Controller Revision History 1.9. NAND Flash Controller Revision History 1.10. SD/eMMC Revision History 1.11. Combo DLL PHY Revision History 1.12. USB 3.1 Gen1 Controller Revision History 1.13. USB 2.0 OTG Controller Revision History 1.14. I3C Controller Revision History 1.15. I2C Controller Revision History 1.16. SPI Controller Revision History 1.17. Timers Revision History 1.18. Watchdog Timers Revision History 1.19. UART Controller Revision History 1.20. GPIO Revision History 1.21. I/O Pin Multiplexing Revision History 1.22. System Manager Revision History 1.23. Clock Manager Revision History 1.24. Reset Manager Revision History 1.25. Power Management Revision History 1.26. Bridges Revision History 1.27. HPS Mailbox Revision History 1.28. MPFE and MPFE-lite Revision History 1.29. EMAC GMII through FPGA Fabric Revision History 1.30. System Interconnect and Firewalls Revision History 1.31. ECC Controller Revision History 1.32. CoreSight* Debug and Trace Revision History 1.33. HPS Register Map Revision History 1.34. Booting and Configuration Revision History 1.35. HPS Use of SDM QSPI Controller Revision History 1.36. Security Revision History
2. Introduction to the Hard Processor System x
2.1. HPS Differences Among Intel SoC Device Families 2.2. HPS Features 2.3. HPS System Integration 2.4. HPS IP Revisions 2.5. HPS Address Map and Register Definitions
2.3. HPS System Integration x
2.3.1. HPS Block Diagram 2.3.2. MPU Features 2.3.3. Application Processor Subsystem 2.3.4. Peripheral Subsystem 2.3.5. System Manager Features 2.3.6. Clock Manager Features 2.3.7. Reset Manager Features 2.3.8. Bridges Features 2.3.9. System Interconnect and Firewalls Features 2.3.10. ECC Controller Features 2.3.11. CoreSight Debug and Trace Features
2.3.2. MPU Features x
2.3.2.1. Arm Cortex-A76 Core Features 2.3.2.2. Arm* Cortex* -A55 Core Features 2.3.2.3. Arm* DynamIQ Shared Unit Features
2.3.3. Application Processor Subsystem x
2.3.3.1. CCU Features 2.3.3.2. GIC Features 2.3.3.3. SMMU Features 2.3.3.4. On-Chip RAM Features
2.3.4. Peripheral Subsystem x
2.3.4.1. EMAC Features 2.3.4.2. DMA Controller Features 2.3.4.3. NAND Flash Controller Features 2.3.4.4. Combo DLL PHY Features 2.3.4.5. USB 3.1 Gen1 Controller Features 2.3.4.6. USB 2.0 OTG Controller Features 2.3.4.7. I3C Controller Features 2.3.4.8. I2C Controller Features 2.3.4.9. SPI Controller Features 2.3.4.10. Timers Features 2.3.4.11. Watchdog Timers Features 2.3.4.12. UART Controller Features 2.3.4.13. GPIO Features 2.3.4.14. I/O Pin Multiplexing Features
2.3.4.1. EMAC Features x
2.3.4.1.1. XGMAC Core 2.3.4.1.2. Time Sensitive Networking 2.3.4.1.3. MAC Transaction Layer 2.3.4.1.4. DMA 2.3.4.1.5. Management Interface 2.3.4.1.6. Synchronized Multidrop Timestamp Gathering Hub 2.3.4.1.7. External Memory 2.3.4.1.8. PHY Interface
3. Micro Processor Unit (MPU) x
3.1. MPU Differences Among Intel SoC Device Families 3.2. MPU Use Cases 3.3. MPU Features 3.4. MPU System Integration 3.5. MPU Arm* Cortex* -A76 Core 3.6. MPU Arm* Cortex* -A55 Core 3.7. MPU Arm* DynamIQ Shared Unit 3.8. MPU Clock Domains 3.9. MPU Reset Domains 3.10. MPU Power Domains 3.11. MPU Address Map and Register Definitions
3.5. MPU Arm* Cortex* -A76 Core x
3.5.1. Arm Cortex-A76 Core Features 3.5.2. System Integration of the Arm* Cortex* -A76 Core 3.5.3. Functional Description of the Arm Cortex-A76 Core
3.5.3. Functional Description of the Arm Cortex-A76 Core x
3.5.3.1. Cortex* -A76 Core Configuration 3.5.3.2. Exception Levels 3.5.3.3. Virtualization 3.5.3.4. Memory Management Unit 3.5.3.5. Level 1 Memory System 3.5.3.6. Level 2 Memory System 3.5.3.7. Generic Interrupt Controller CPU Interface 3.5.3.8. Advanced Single Instruction Multiple Data and Floating Point Support 3.5.3.9. Cryptographic Extensions 3.5.3.10. Generic Timer 3.5.3.11. Cache Protection 3.5.3.12. Debug
3.5.3.2. Exception Levels x
3.5.3.2.1. Security State 3.5.3.2.2. Security Model
3.5.3.4. Memory Management Unit x
3.5.3.4.1. Translation Lookaside Buffer 3.5.3.4.2. Translation Match Process 3.5.3.4.3. Translation Table Walks
3.5.3.5. Level 1 Memory System x
3.5.3.5.1. Instruction Cache 3.5.3.5.2. Data Cache 3.5.3.5.3. Data Prefetching
3.5.3.11. Cache Protection x
3.5.3.11.1. Uncorrected Errors and Data Poisoning 3.5.3.11.2. Reliability, Availability, and Serviceability Error Types 3.5.3.11.3. Error Recording 3.5.3.11.4. Error Injection
3.5.3.12. Debug x
3.5.3.12.1. Breakpoints and Watchpoints 3.5.3.12.2. Performance Monitoring Unit 3.5.3.12.3. Activity Monitor Unit 3.5.3.12.4. Embedded Trace Macrocell
3.6. MPU Arm* Cortex* -A55 Core x
3.6.1. Arm* Cortex* -A55 Core Features 3.6.2. System Integration of the Arm* Cortex* -A55 Core 3.6.3. Functional Description of the Arm* Cortex* -A55 Core
3.6.3. Functional Description of the Arm* Cortex* -A55 Core x
3.6.3.1. Cortex* -A55 Core Configuration 3.6.3.2. Exception Levels 3.6.3.3. Virtualization 3.6.3.4. Memory Management Unit 3.6.3.5. Level 1 Memory System 3.6.3.6. Level 2 Memory System 3.6.3.7. Generic Interrupt Controller CPU Interface 3.6.3.8. Data Processing Unit 3.6.3.9. Generic Timer 3.6.3.10. Cache Protection 3.6.3.11. Debug
3.6.3.2. Exception Levels x
3.6.3.2.1. Security State 3.6.3.2.2. Security Model
3.6.3.4. Memory Management Unit x
3.6.3.4.1. Translation Lookaside Buffer 3.6.3.4.2. Translation Match Process 3.6.3.4.3. Translation Table Walks
3.6.3.10. Cache Protection x
3.6.3.10.1. Uncorrected Errors and Data Poisoning 3.6.3.10.2. Reliability, Availability and Serviceability Error Types 3.6.3.10.3. Error Reporting 3.6.3.10.4. Error Injection
3.6.3.11. Debug x
3.6.3.11.1. Breakpoints and Watchpoints 3.6.3.11.2. Performance Monitoring Unit 3.6.3.11.3. Embedded Trace Macrocell
3.7. MPU Arm* DynamIQ Shared Unit x
3.7.1. Arm* DynamIQ Shared Unit Features 3.7.2. System Integration of the Arm* DynamIQ Shared Unit 3.7.3. Functional Description of the Arm* DynamIQ Shared Unit
3.7.3. Functional Description of the Arm* DynamIQ Shared Unit x
3.7.3.1. DSU Configuration 3.7.3.2. Level 3 Cache 3.7.3.3. Interfaces 3.7.3.4. Debug
3.7.3.2. Level 3 Cache x
3.7.3.2.1. Cache Allocation Policy 3.7.3.2.2. Cache Partitioning 3.7.3.2.3. Cache Data RAM Latency 3.7.3.2.4. Cache Slices and Portions
3.7.3.4. Debug x
3.7.3.4.1. DebugBlock 3.7.3.4.2. Embedded Cross Trigger 3.7.3.4.3. Performance Monitoring Unit
4. Application Processor Subsystem x
4.1. Cache Coherency Unit (CCU) 4.2. Generic Interrupt Controller (GIC) 4.3. System Memory Management Unit (SMMU) 4.4. On-Chip RAM
4.1. Cache Coherency Unit (CCU) x
4.1.1. CCU Differences Among Intel SoC Device Families 4.1.2. CCU Use Cases 4.1.3. CCU Features 4.1.4. CCU System Integration 4.1.5. CCU Functional Description 4.1.6. CCU Programming Model 4.1.7. CCU Address Map and Register Definitions
4.1.5. CCU Functional Description x
4.1.5.1. Block Diagram 4.1.5.2. Ports 4.1.5.3. Cache Coherency Protocol 4.1.5.4. Addressing and Memory Regions 4.1.5.5. Connectivity 4.1.5.6. Snoop Filters 4.1.5.7. System Memory Cache 4.1.5.8. Credits and Resources 4.1.5.9. Quality of Service 4.1.5.10. Storage Protection 4.1.5.11. Exclusive Monitors 4.1.5.12. Firewall and Security 4.1.5.13. Interrupts 4.1.5.14. Clocks 4.1.5.15. Resets 4.1.5.16. Power Management 4.1.5.17. Shutdown of Interfaces 4.1.5.18. Error Handling 4.1.5.19. CCU Restrictions
4.1.5.1. Block Diagram x
4.1.5.1.1. Coherent Agent Interface Unit (CAIU) 4.1.5.1.2. Non-coherent Agent Interface Unit (NCAIU) 4.1.5.1.3. Distributed Coherence Engine (DCE) 4.1.5.1.4. Distributed Memory Interface (DMI) 4.1.5.1.5. Distributed Virtual Memory Engine (DVE) 4.1.5.1.6. Distributed I/O Interface (DII)
4.1.5.2. Ports x
4.1.5.2.1. DSU CHI-B Initiator Port 4.1.5.2.2. F2H ACE-Lite Initiator Port 4.1.5.2.3. GIC_M ACE-lite Initiator Port 4.1.5.2.4. TCU Ace-lite+DVM Initiator Port 4.1.5.2.5. CCU_IOM ACE-Lite Initiator Port 4.1.5.2.6. CCU_DMI0, CCU_DMI1 1AXI4 Target Ports 4.1.5.2.7. CCU_IOS AXI Target Port 4.1.5.2.8. MPFE CSR AXI Target Port 4.1.5.2.9. GIC AXI Target Port 4.1.5.2.10. OCRAM AXI Target Port
4.1.5.3. Cache Coherency Protocol x
4.1.5.3.1. Coherent Read Request 4.1.5.3.2. Coherent Clean Request 4.1.5.3.3. Coherent Write Request
4.1.5.4. Addressing and Memory Regions x
4.1.5.4.1. Ncore Register Space 4.1.5.4.2. General Purpose Address Space 4.1.5.4.3. Boot Address Space 4.1.5.4.4. Interleaving
4.1.5.4.2. General Purpose Address Space x
4.1.5.4.2.1. Address Map When Using a Single SDRAM Channel 4.1.5.4.2.2. Address Map When Using Multiple SDRAM Channels
4.1.5.12. Firewall and Security x
4.1.5.12.1. OCRAM Firewall 4.1.5.12.2. GIC Firewall 4.1.5.12.3. Service Network Access 4.1.5.12.4. AXI APROT Tunneling
4.1.5.15. Resets x
4.1.5.15.1. Q-Channel
4.1.5.18. Error Handling x
4.1.5.18.1. Correctable Errors 4.1.5.18.2. Uncorrectable Errors
4.1.5.19. CCU Restrictions x
4.1.5.19.1. CHI Support 4.1.5.19.2. AXI and ACE Support 4.1.5.19.3. Ordering Support
4.1.6. CCU Programming Model x
4.1.6.1. CCU Initialization 4.1.6.2. Boot Region CSR Default Settings 4.1.6.3. Error Registers
4.1.6.1. CCU Initialization x
4.1.6.1.1. Address Space Configuration 4.1.6.1.2. SMC Configuration
4.2. Generic Interrupt Controller (GIC) x
4.2.1. GIC Differences Among Intel® SoC Device Families 4.2.2. GIC Features 4.2.3. GIC System Integration 4.2.4. GIC Functional Description 4.2.5. GIC Programming Model 4.2.6. GIC Address Map and Register Definitions
4.2.4. GIC Functional Description x
4.2.4.1. Types of Interrupts 4.2.4.2. Clock Domains 4.2.4.3. Reset Domains
4.2.5. GIC Programming Model x
4.2.5.1. GIC Shared Peripheral Interrupts Map for the SoC HPS
4.3. System Memory Management Unit (SMMU) x
4.3.1. SMMU Differences Among Intel SoC Device Families 4.3.2. SMMU Use Cases 4.3.3. SMMU Features 4.3.4. SMMU System Integration 4.3.5. SMMU Signal Description 4.3.6. SMMU Functional Description 4.3.7. SMMU Programming Model 4.3.8. SMMU Address Map and Register Definitions 4.3.9. SMMU Design Guidelines and Examples
4.3.3. SMMU Features x
4.3.3.1. DTI Interface for TCU 4.3.3.2. Stage2 Translation 4.3.3.3. TLB 4.3.3.4. Bypass Mode 4.3.3.5. APB4 Programming Interface
4.3.4. SMMU System Integration x
4.3.4.1. TBU Instances 4.3.4.2. DTI Interconnect Topology 4.3.4.3. MMU-600 interfaces 4.3.4.4. IP Configuration
4.3.4.3. MMU-600 interfaces x
4.3.4.3.1. TCU Interfaces 4.3.4.3.2. TBU Interfaces 4.3.4.3.3. DTI Interconnect Interfaces
4.3.4.3.1. TCU Interfaces x
4.3.4.3.1.1. APB4 Programming Interface 4.3.4.3.1.2. ACE-Lite Manager for Table walk and DVM for TCU 4.3.4.3.1.3. LPI Interfaces for TCU 4.3.4.3.1.4. DTI Interface for TCU 4.3.4.3.1.5. SYSCO Interface for TCU 4.3.4.3.1.6. PMU snapshot Interface for TCU
4.3.4.3.2. TBU Interfaces x
4.3.4.3.2.1. ACE-Lite Subordinate Interface 4.3.4.3.2.2. ACE-Lite Manager Interface 4.3.4.3.2.3. DTI interface for TBU 4.3.4.3.2.4. LPI Interfaces for TBU 4.3.4.3.2.5. Interrupt Interfaces for TBU
4.3.4.3.3. DTI Interconnect Interfaces x
4.3.4.3.3.1. DTI Interconnect Switch Interfaces 4.3.4.3.3.2. DTI Interconnect Sizer Interfaces 4.3.4.3.3.3. DTI Interconnect Register Slice Interfaces
4.3.4.4. IP Configuration x
4.3.4.4.1. MMU-600 TCU Hardware Configuration 4.3.4.4.2. MMU-600 TBU Hardware Configurations 4.3.4.4.3. MMU-600 DTI Switch Hardware Configuration 4.3.4.4.4. MMU-600 DTI Async Bridge configuration
4.3.5. SMMU Signal Description x
4.3.5.1. MMU-600 TCU Configuration Signals 4.3.5.2. MMU-600 TBU Configuration Signals 4.3.5.3. TBU with Untranslated Interface
4.3.6. SMMU Functional Description x
4.3.6.1. Block Diagram 4.3.6.2. Functional Blocks 4.3.6.3. Functional Modes 4.3.6.4. Interrupts
4.3.6.3. Functional Modes x
4.3.6.3.1. Address Translation 4.3.6.3.2. Stage1 Translation 4.3.6.3.3. Stage2 Translation 4.3.6.3.4. TLB 4.3.6.3.5. Bypass Mode
4.3.6.4. Interrupts x
4.3.6.4.1. Interrupt Interfaces for TBU
4.3.7. SMMU Programming Model x
4.3.7.1. Initializing the SMMU 4.3.7.2. Assigning Stream IDs 4.3.7.3. Allocating the Command Queue 4.3.7.4. Allocating the Event Queue 4.3.7.5. Configuring the Stream Table 4.3.7.6. Initializing the Command Queue 4.3.7.7. Initializing the Event Queue 4.3.7.8. Invalidate TLBs and Configuration caches 4.3.7.9. Create Context Descriptor 4.3.7.10. Creating Stream Table Entry 4.3.7.11. Enabling the SMMU
4.3.8. SMMU Address Map and Register Definitions x
4.3.8.1. TBU Private Registers
4.3.8.1. TBU Private Registers x
4.3.8.1.1. TBU Stream Control Register[m][n] 4.3.8.1.2. TBU Stream ID Ax Register[m][n]
4.3.9. SMMU Design Guidelines and Examples x
4.3.9.1. F2SDRAM_TBU Special Handling 4.3.9.2. Translation Table Walk Sequence
4.3.9.2. Translation Table Walk Sequence x
4.3.9.2.1. Calculating Page Table Walks
4.4. On-Chip RAM x
4.4.1. On-Chip RAM Differences Among Intel SoC Device Families 4.4.2. On-Chip RAM Use Cases 4.4.3. On-Chip RAM Features 4.4.4. On-Chip RAM Functional Description 4.4.5. On-Chip RAM Address Map and Register Definitions
4.4.4. On-Chip RAM Functional Description x
4.4.4.1. Read and Write Double-Bit Bus Errors 4.4.4.2. On-Chip RAM Controller 4.4.4.3. On-Chip RAM Burst Support 4.4.4.4. Exclusive Access Support 4.4.4.5. Sub-word Accesses 4.4.4.6. On-Chip RAM Clocks 4.4.4.7. On-Chip RAM Resets 4.4.4.8. On-Chip RAM Initialization 4.4.4.9. ECC Protection
4.4.4.5. Sub-word Accesses x
4.4.4.5.1. Pipeline and Timing
5. Peripheral Subsystem x
5.1. Ethernet Media Access Controller 5.2. DMA Controller 5.3. NAND Flash Controller 5.4. SD/eMMC Host Controller 5.5. Combo DLL PHY 5.6. USB 3.1 Gen1 Controller 5.7. USB 2.0 OTG Controller 5.8. I3C Controller 5.9. I2C Controller 5.10. SPI Controller 5.11. Timers 5.12. Watchdog Timers 5.13. UART Controller 5.14. General-Purpose I/O Interface (GPIO) 5.15. Hard Processor System I/O Pin Multiplexing
5.1. Ethernet Media Access Controller x
5.1.1. EMAC Differences Among Intel SoC Device Families 5.1.2. EMAC Use Cases 5.1.3. EMAC Features 5.1.4. EMAC System Integration 5.1.5. EMAC Signal Description and Interfaces 5.1.6. EMAC Functional Description 5.1.7. EMAC Programming Model 5.1.8. EMAC Address Map and Register Definitions 5.1.9. EMAC Design Guidelines and Examples
5.1.3. EMAC Features x
5.1.3.1. XGMAC Core 5.1.3.2. Time Sensitive Networking 5.1.3.3. MAC Transaction Layer 5.1.3.4. DMA 5.1.3.5. Management Interface 5.1.3.6. Synchronized Multidrop Timestamp Gathering Hub 5.1.3.7. External Memory 5.1.3.8. PHY Interface
5.1.4. EMAC System Integration x
5.1.4.1. EMAC Block Diagram and Overview 5.1.4.2. EMAC System Integration
5.1.5. EMAC Signal Description and Interfaces x
5.1.5.1. HPS EMAC I/O Signals 5.1.5.2. FPGA EMAC I/O Signals 5.1.5.3. PHY Management Interface 5.1.5.4. SMTG Hub Signals and Interface 5.1.5.5. Timestamp Interface Signals 5.1.5.6. DMA Host Interface 5.1.5.7. System Manager Configuration Interface
5.1.5.3. PHY Management Interface x
5.1.5.3.1. MDIO Interface 5.1.5.3.2. I2C External PHY Management Interface
5.1.6. EMAC Functional Description x
5.1.6.1. External Memory 5.1.6.2. DMA Controller 5.1.6.3. Descriptor 5.1.6.4. Checksum Offload Engine (COE) 5.1.6.5. TCP Segmentation Offload 5.1.6.6. Packet Filtering 5.1.6.7. Management Counter 5.1.6.8. Flow Control 5.1.6.9. IEEE 1588-2008 Advanced Timestamp 5.1.6.10. TSN Features 5.1.6.11. SMTG Hub Time of Day Synchronization 5.1.6.12. Clocks 5.1.6.13. Resets 5.1.6.14. Interrupts
5.1.6.1. External Memory x
5.1.6.1.1. Transmit and Receive Data FIFO Buffers 5.1.6.1.2. TCP/IP Segmentation Offload Memory 5.1.6.1.3. Descriptor Cache Memory 5.1.6.1.4. Gate Control List Memory
5.1.6.2. DMA Controller x
5.1.6.2.1. Application Bus Burst Access 5.1.6.2.2. Application Data Buffer Alignment 5.1.6.2.3. Buffer Size Calculations 5.1.6.2.4. DMA Descriptor Fetch Operation 5.1.6.2.5. DMA TX Data Transfer Operation 5.1.6.2.6. DMA RX Data Transfer Operation 5.1.6.2.7. DMA Descriptor Write-Back Operation 5.1.6.2.8. DMA Start/Stop Operation 5.1.6.2.9. Memory Cache Size Requirements 5.1.6.2.10. Memory Cache Access Arbitration 5.1.6.2.11. DMA Error Handling
5.1.6.2.11. DMA Error Handling x
5.1.6.2.11.1. TX DMA Bus Error Handling Flow 5.1.6.2.11.2. RX DMA Bus Error Handling Flow
5.1.6.3. Descriptor x
5.1.6.3.1. Descriptor Structure 5.1.6.3.2. Descriptor Endianness 5.1.6.3.3. Transmit Descriptor 5.1.6.3.4. Receive Descriptor Receive Normal Descriptor (Read Format) Receive Normal Descriptor (Write-Back Format) Receive Context Descriptor (Write-Back Format) 5.1.6.3.5. Enhanced Descriptor for Time-Based Scheduling 5.1.6.3.6. Header Payload Split Support
5.1.6.5. TCP Segmentation Offload x
5.1.6.5.1. Description of the TSO Feature 5.1.6.5.2. DMA Operation with TSO Feature 5.1.6.5.3. TCP/IP Header Fields 5.1.6.5.4. Header and Payload Fields of Segmented Packets 5.1.6.5.5. Context Descriptor Sequence
5.1.6.6. Packet Filtering x
5.1.6.6.1. Source Address or Destination Address Filtering 5.1.6.6.2. VLAN Filtering 5.1.6.6.3. Extended VLAN Filtering 5.1.6.6.4. Layer 3 and Layer 4 Match Filtering
5.1.6.8. Flow Control x
5.1.6.8.1. Transmit Flow Control 5.1.6.8.2. Receive Flow Control
5.1.6.9. IEEE 1588-2008 Advanced Timestamp x
5.1.6.9.1. Delay Request-Response Mechanism 5.1.6.9.2. Peer-to-Peer PTP Transparent Clock Message Support 5.1.6.9.3. Clock Types 5.1.6.9.4. Reference Timing Source 5.1.6.9.5. System Time Register Module 5.1.6.9.6. Transmit Path Functions 5.1.6.9.7. Receive Path Functions
5.1.6.10. TSN Features x
5.1.6.10.1. Enhancements to Scheduled Traffic 5.1.6.10.2. Frame Preemption 5.1.6.10.3. Time-Based Scheduling 5.1.6.10.4. Credit Based Shaper
5.1.6.11. SMTG Hub Time of Day Synchronization x
5.1.6.11.1. SMTG Hub Overview 5.1.6.11.2. SMTG Hub Logic 5.1.6.11.3. SMTG Hub Integration with the HPS and FPGA
5.1.6.12. Clocks x
5.1.6.12.1. Clock Domain
5.1.6.13. Resets x
5.1.6.13.1. EMAC ECC RAM Reset 5.1.6.13.2. EMAC Software Reset
5.1.7. EMAC Programming Model x
5.1.7.1. System Level EMAC configurable Registers 5.1.7.2. EMAC HPS Interface Initialization 5.1.7.3. EMAC FPGA Interface Initialization 5.1.7.4. DMA Initialization 5.1.7.5. EMAC Initialization and Configuration 5.1.7.6. Performing Normal Receive and Transmit Operation 5.1.7.7. Stopping and Starting Transmission 5.1.7.8. Reconfiguring the DMA Registers 5.1.7.9. Switching to a New Descriptor List in the Receive DMA 5.1.7.10. Handling Bus Errors and Recovery 5.1.7.11. Setting up TCP Segmentation Offload 5.1.7.12. Setting up VLAN Filtering on Receive 5.1.7.13. Setting up Extended VLAN Filtering 5.1.7.14. Setting up the L3-L4 Filtering 5.1.7.15. Programming the SMTG Hub 5.1.7.16. Setting up the IEEE 1588 PTP Timestamping 5.1.7.17. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output 5.1.7.18. Programming the GCL and GCL Linked Registers 5.1.7.19. Programming Guidelines for EST 5.1.7.20. Enabling the Frame Preemption Function 5.1.7.21. Setting up the Time-Based Scheduling Function
5.1.7.1. System Level EMAC configurable Registers x
5.1.7.1.1. System Manager Configurable Registers 5.1.7.1.2. Clock Manager Configurable Registers 5.1.7.1.3. Reset Manager Configurable Registers
5.1.7.10. Handling Bus Errors and Recovery x
5.1.7.10.1. Transmit DMA Channel 5.1.7.10.2. Receive DMA Channel
5.1.7.14. Setting up the L3-L4 Filtering x
5.1.7.14.1. Writing to the Indirect Addressed Registers 5.1.7.14.2. Reading the Indirect Addressed Registers
5.1.7.16. Setting up the IEEE 1588 PTP Timestamping x
5.1.7.16.1. Initialization Guidelines for System Time Generation 5.1.7.16.2. Coarse Correction Method 5.1.7.16.3. Fine-Correction Method
5.1.7.17. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output x
5.1.7.17.1. Generating a Single Pulse on PPS 5.1.7.17.2. Generating a Pulse Train on PPS 5.1.7.17.3. Generating an Interrupt without Affecting the PPS
5.1.7.20. Enabling the Frame Preemption Function x
5.1.7.20.1. Receive Side Programming 5.1.7.20.2. Transmit Side Programming
5.1.9. EMAC Design Guidelines and Examples x
5.1.9.1. HPS RGMII System Integration 5.1.9.2. Interface to HPS IO Pins 5.1.9.3. RGMII Clock Skew Guidelines
5.1.9.3. RGMII Clock Skew Guidelines x
5.1.9.3.1. Use Case 1 – Utilize Programmable HPS I/O Delay Feature 5.1.9.3.2. Use Case 2 – Configure External PHY RGMII-Internal Delay (RGMII-ID) 5.1.9.3.3. Use Case 3 – Introduce Board Trace Delay
5.2. DMA Controller x
5.2.1. DMA Controller Differences Among Intel SoC Device Families 5.2.2. DMA Controller Use Cases 5.2.3. DMA Controller Features 5.2.4. DMA Controller System Integration 5.2.5. DMA Controller Functional Description 5.2.6. DMA Controller Address Map and Register Definitions
5.2.5. DMA Controller Functional Description x
5.2.5.1. Flow Control 5.2.5.2. Handshaking Interface 5.2.5.3. Interrupt Outputs 5.2.5.4. DMA Controller Peripheral Request Interface
5.2.5.4. DMA Controller Peripheral Request Interface x
5.2.5.4.1. Peripheral Request Interface Mapping
5.3. NAND Flash Controller x
5.3.1. NAND Flash Controller Differences Among Intel SoC Device Families 5.3.2. NAND Flash Controller Use Cases 5.3.3. NAND Flash Controller Features 5.3.4. NAND Flash Controller System Integration 5.3.5. NAND Flash Controller Signal Description 5.3.6. NAND Flash Controller Functional Description 5.3.7. NAND Flash Controller Programming Model 5.3.8. NAND Flash Controller Address Map and Register Definitions
5.3.5. NAND Flash Controller Signal Description x
5.3.5.1. Device Discovery Interface 5.3.5.2. Write Protection Interface 5.3.5.3. Interrupt Interface 5.3.5.4. DFI Interface
5.3.6. NAND Flash Controller Functional Description x
5.3.6.1. Block Diagram 5.3.6.2. Initialization Protocol (Device Discovery) 5.3.6.3. NAND Flash Addressing and Data Layout 5.3.6.4. Command Engine Functionality 5.3.6.5. ECC Engine Functionality 5.3.6.6. Control Data Mechanism 5.3.6.7. Remapping Mechanism 5.3.6.8. Write Protection Mechanism 5.3.6.9. Error and Special Scenarios Handling 5.3.6.10. Controller Fixed Parameters and Clock Frequencies Supported
5.3.6.3. NAND Flash Addressing and Data Layout x
5.3.6.3.1. NAND Flash Addressing 5.3.6.3.2. Data Layout 5.3.6.3.3. Layout Between Pages
5.3.6.4. Command Engine Functionality x
5.3.6.4.1. Command Engine Architecture 5.3.6.4.2. CDMA Work Mode 5.3.6.4.3. PIO Work Mode 5.3.6.4.4. Generic Work Mode 5.3.6.4.5. Extended Functionality in Command Engine
5.3.6.4.2. CDMA Work Mode x
5.3.6.4.2.1. Operation in CDMA Mode 5.3.6.4.2.2. Thread Synchronization Mechanism 5.3.6.4.2.3. NOP Descriptor
5.3.6.4.3. PIO Work Mode x
5.3.6.4.3.1. Operation in PIO Work Mode 5.3.6.4.3.2. Last Operation Status
5.3.6.4.4. Generic Work Mode x
5.3.6.4.4.1. Operation in Generic Work Mode 5.3.6.4.4.2. Last Operation Status 5.3.6.4.4.3. Switching To/From Generic Work Mode
5.3.6.4.5. Extended Functionality in Command Engine x
5.3.6.4.5.1. LUN Interleaving 5.3.6.4.5.2. Multipage Commands 5.3.6.4.5.3. Cache Commands 5.3.6.4.5.4. Multi-plane Commands 5.3.6.4.5.5. Thread Reset Commands 5.3.6.4.5.6. Timeout Functionality 5.3.6.4.5.7. Support of TLC (pSLC Mode) Devices
5.3.6.5. ECC Engine Functionality x
5.3.6.5.1. Error Correction 5.3.6.5.2. Sector Sizes 5.3.6.5.3. Bad Block Marker 5.3.6.5.4. Scrambling Support 5.3.6.5.5. Erased Page Detection Support
5.3.6.9. Error and Special Scenarios Handling x
5.3.6.9.1. Access to Protected Areas 5.3.6.9.2. Bus Error 5.3.6.9.3. NAND Device Error 5.3.6.9.4. Data Integrity Errors 5.3.6.9.5. ECC Errors 5.3.6.9.6. Descriptor/Command Error 5.3.6.9.7. DQS Error 5.3.6.9.8. Error Interrupt Generation 5.3.6.9.9. Recommended Error Handling Checking Software Flow
5.3.7. NAND Flash Controller Programming Model x
5.3.7.1. NAND Controller Registers Programming Model 5.3.7.2. Status Polling Configuration 5.3.7.3. Device Layout Configuration 5.3.7.4. Configure Multiplane and Cache Operations 5.3.7.5. ECC Enabling 5.3.7.6. Interrupts Configuration 5.3.7.7. Configuring Timing Registers 5.3.7.8. Switch from SDR to DDR Operation Mode 5.3.7.9. Switch from DDR to SDR Operation Mode 5.3.7.10. Slave DMA Programming 5.3.7.11. Data Pre-Fetching Mechanism 5.3.7.12. Data Integrity Mechanism 5.3.7.13. Enabling pSLC Mode for the TLC Devices
5.3.7.1. NAND Controller Registers Programming Model x
5.3.7.1.1. Programming SFR Registers 5.3.7.1.2. Programming Command Registers
5.4. SD/eMMC Host Controller x
5.4.1. SD/eMMC Differences Among Intel SoC Device Families 5.4.2. SD/eMMC Use Cases 5.4.3. SD/eMMC Features 5.4.4. SD/eMMC System Integration 5.4.5. SD/eMMC Signal Description 5.4.6. SD/eMMC Functional Description 5.4.7. SD/eMMC Programming Model 5.4.8. SD/eMMC Address Map and Register Definitions 5.4.9. SD/eMMC Design Guidelines and Examples
5.4.3. SD/eMMC Features x
5.4.3.1. Supported Standards 5.4.3.2. SD Support 5.4.3.3. eMMC Support 5.4.3.4. DMA Support
5.4.6. SD/eMMC Functional Description x
5.4.6.1. Block Diagram 5.4.6.2. Configuration 5.4.6.3. DMA Operation 5.4.6.4. Clocks 5.4.6.5. Resets 5.4.6.6. SD Voltage Switching 5.4.6.7. Timings on the SD/eMMC Interface 5.4.6.8. Command Queuing
5.4.6.1. Block Diagram x
5.4.6.1.1. Bus Interface Unit 5.4.6.1.2. Reset Control Module 5.4.6.1.3. Synchronization Module 5.4.6.1.4. Response Module 5.4.6.1.5. FIFO Interface Unit 5.4.6.1.6. Card Interface Unit 5.4.6.1.7. System Requester Interface 5.4.6.1.8. System Manager Interface 5.4.6.1.9. Host Settings Interface 5.4.6.1.10. Command Queue Settings
5.4.6.2. Configuration x
5.4.6.2.1. Host Capabilities
5.4.6.3. DMA Operation x
5.4.6.3.1. SDMA Operation 5.4.6.3.2. ADMA2 Operation 5.4.6.3.3. ADMA3 Operation 5.4.6.3.4. DMA Errors
5.4.6.5. Resets x
5.4.6.5.1. Controller Software Reset
5.4.6.7. Timings on the SD/eMMC Interface x
5.4.6.7.1. Tuning
5.4.6.7.1. Tuning x
5.4.6.7.1.1. Tuning Sequence for SD 5.4.6.7.1.2. Tuning Sequence for eMMC
5.4.6.8. Command Queuing x
5.4.6.8.1. Optional Modes of Operation 5.4.6.8.2. Task Execution Order
5.4.7. SD/eMMC Programming Model x
5.4.7.1. Combo PHY Register Interface 5.4.7.2. Pre-Initialization Sequence 5.4.7.3. Error Handling
5.4.7.1. Combo PHY Register Interface x
5.4.7.1.1. Read Access 5.4.7.1.2. Write Access
5.4.7.3. Error Handling x
5.4.7.3.1. Generic Operation Error Recovery 5.4.7.3.2. Command Queueing Error Recovery 5.4.7.3.3. Combo PHY Underrun/Overflow Error Recovery
5.4.9. SD/eMMC Design Guidelines and Examples x
5.4.9.1. SD Card Level Shifting
5.5. Combo DLL PHY x
5.5.1. Combo DLL PHY Differences Among Intel SoC Device Families 5.5.2. Combo DLL PHY Use Cases 5.5.3. Combo DLL PHY Features 5.5.4. Combo DLL PHY System Integration 5.5.5. Combo DLL PHY Signal Description 5.5.6. Combo DLL PHY Functional Description 5.5.7. Combo DLL PHY Programming Model 5.5.8. Combo DLL PHY Address Map and Register Definitions
5.5.6. Combo DLL PHY Functional Description x
5.5.6.1. Block Diagram 5.5.6.2. Operation Modes 5.5.6.3. Clocking 5.5.6.4. DLL Functionality 5.5.6.5. Write Data Path 5.5.6.6. Read Data Path 5.5.6.7. Generation of CE#, CLE, ALE, WP#, and RE# signals 5.5.6.8. Resets
5.5.6.4. DLL Functionality x
5.5.6.4.1. DLL Locking
5.5.6.5. Write Data Path x
5.5.6.5.1. DQS Write Signal Generation 5.5.6.5.2. Output Enable Signal Generation
5.5.6.6. Read Data Path x
5.5.6.6.1. Generation of Dynamic Termination Signal 5.5.6.6.2. Input Enable Signal Generation
5.5.7. Combo DLL PHY Programming Model x
5.5.7.1. Initialization Procedure 5.5.7.2. DLL Lock Debugging 5.5.7.3. DLL Secondary Delay Configuration 5.5.7.4. Handling FIFO DQS Overflow and Underrun 5.5.7.5. Tuning for SD/eMMC Interface
5.6. USB 3.1 Gen1 Controller x
5.6.1. USB 3.1 Gen1 Controller Differences Among Intel SoC Device Families 5.6.2. USB 3.1 Gen1 Controller Use Cases 5.6.3. USB 3.1 Gen1 Controller Features 5.6.4. USB 3.1 Gen1 Controller System Integration 5.6.5. USB 3.1 Gen1 Controller Functional Description 5.6.6. USB 3.1 Gen1 Controller Programming Model 5.6.7. USB 3.1 Gen1 Controller Address Map and Register Definitions 5.6.8. USB 3.1 Gen1 Controller Design Guidelines and Examples
5.6.3. USB 3.1 Gen1 Controller Features x
5.6.3.1. Unsupported Features
5.6.5. USB 3.1 Gen1 Controller Functional Description x
5.6.5.1. Manager Interface 5.6.5.2. AHB Subordinate Interface 5.6.5.3. Application interface Unit 5.6.5.4. Bus Management Unit 5.6.5.5. Packet FIFO Controller 5.6.5.6. RAM 5.6.5.7. MAC 5.6.5.8. DMA 5.6.5.9. Loopback 5.6.5.10. PHY Interfaces 5.6.5.11. USB 3.1 Gen1 Controller Clocks 5.6.5.12. USB 3.1 Gen1 Controller Resets
5.6.5.1. Manager Interface x
5.6.5.1.1. AXI Manager Interface
5.6.5.8. DMA x
5.6.5.8.1. Reception Flow Details 5.6.5.8.2. Transmission Flow Details
5.6.5.9. Loopback x
5.6.5.9.1. Software Loopback Mode 5.6.5.9.2. BIST Loopback Mode
5.6.5.10. PHY Interfaces x
5.6.5.10.1. USB 2.0 ULPI PHY 5.6.5.10.2. PIPE Interface 5.6.5.10.3. USB 3.1 Mode-switch Controller 5.6.5.10.4. USB Type-C Receptacle 5.6.5.10.5. Performance 5.6.5.10.6. Maximum USB Bandwidth
5.6.5.10.1. USB 2.0 ULPI PHY x
5.6.5.10.1.1. Signals
5.6.5.10.2. PIPE Interface x
5.6.5.10.2.1. IO Connection
5.6.5.10.3. USB 3.1 Mode-switch Controller x
5.6.5.10.3.1. USB3.1 Mode-switch Controller Signals
5.6.5.11. USB 3.1 Gen1 Controller Clocks x
5.6.5.11.1. Clock Enable 5.6.5.11.2. Clock Gating
5.6.5.12. USB 3.1 Gen1 Controller Resets x
5.6.5.12.1. Reset Requirements 5.6.5.12.2. Software Resets 5.6.5.12.3. Warm Reset
5.6.6. USB 3.1 Gen1 Controller Programming Model x
5.6.6.1. Programming Controller in Host Mode 5.6.6.2. Programming Controller in Device Mode
5.6.6.1. Programming Controller in Host Mode x
5.6.6.1.1. Initialization Phase 5.6.6.1.2. Host Controller Capability Registers 5.6.6.1.3. Programming Model 5.6.6.1.4. Device Initialization
5.6.6.2. Programming Controller in Device Mode x
5.6.6.2.1. Device Power-on or Soft Reset 5.6.6.2.2. Initialization on USB Reset 5.6.6.2.3. Initialization on Connect Done 5.6.6.2.4. Initialization on SetAddress Request 5.6.6.2.5. Initialization on SetConfiguration or SetInterface Request 5.6.6.2.6. Agilex 5 Programming Model 5.6.6.2.7. Controller as Host
5.6.8. USB 3.1 Gen1 Controller Design Guidelines and Examples x
5.6.8.1. USB 3.1 Gen1 Controller Wakeup and Power Control
5.7. USB 2.0 OTG Controller x
5.7.1. USB 2.0 OTG Controller Differences Among Intel SoC Device Families 5.7.2. USB 2.0 OTG Controller Use Cases 5.7.3. USB 2.0 OTG Controller Features 5.7.4. USB 2.0 OTG Controller System Integration 5.7.5. USB 2.0 OTG Controller Functional Description 5.7.6. USB 2.0 OTG Controller Programming Model 5.7.7. USB 2.0 OTG Controller Address Map and Register Definitions
5.7.4. USB 2.0 OTG Controller System Integration x
5.7.4.1. USB 2.0 ULPI PHY Signal Description
5.7.5. USB 2.0 OTG Controller Functional Description x
5.7.5.1. Distributed Virtual Memory Support 5.7.5.2. Initiator Interface 5.7.5.3. Target Interface 5.7.5.4. USB OTG Controller Components 5.7.5.5. DMA 5.7.5.6. Local Memory Buffer 5.7.5.7. Clocks 5.7.5.8. Resets 5.7.5.9. Interrupts
5.7.5.4. USB OTG Controller Components x
5.7.5.4.1. Application Interface Unit 5.7.5.4.2. Packet FIFO Controller 5.7.5.4.3. SPRAM 5.7.5.4.4. MAC 5.7.5.4.5. Wakeup and Power Control 5.7.5.4.6. PHY Interface Unit
5.7.5.4.4. MAC x
5.7.5.4.4.1. USB Transactions 5.7.5.4.4.2. Host Protocol 5.7.5.4.4.3. Device Protocol 5.7.5.4.4.4. OTG Protocol
5.7.5.7. Clocks x
5.7.5.7.1. Clock Gating
5.7.5.8. Resets x
5.7.5.8.1. Reset Requirements 5.7.5.8.2. Hardware Reset 5.7.5.8.3. Software Reset 5.7.5.8.4. Taking the USB 2.0 OTG Controller Out of Reset
5.7.6. USB 2.0 OTG Controller Programming Model x
5.7.6.1. Enabling SPRAM ECCs 5.7.6.2. Host Initialization 5.7.6.3. Host Transaction 5.7.6.4. Device Initialization 5.7.6.5. Device Transaction
5.7.6.5. Device Transaction x
5.7.6.5.1. IN Transactions 5.7.6.5.2. OUT Transactions 5.7.6.5.3. Control Transfers
5.8. I3C Controller x
5.8.1. I3C Controller Differences Among Intel SoC Device Families 5.8.2. I3C Controller Use Cases 5.8.3. I3C Controller Features 5.8.4. I3C Controller System Integration 5.8.5. I3C Controller Signal Description 5.8.6. I3C Controller Functional Description 5.8.7. I3C Controller Programming Model 5.8.8. I3C Controller Address Map and Register Definitions 5.8.9. I3C Controller Design Guidelines and Examples
5.8.5. I3C Controller Signal Description x
5.8.5.1. Interface to HPS I/O 5.8.5.2. FPGA Routing
5.8.6. I3C Controller Functional Description x
5.8.6.1. Device Address 5.8.6.2. In-Band Interrupt (IBI) 5.8.6.3. Simple-Transfer DMA (SDMA) Handshake 5.8.6.4. Interrupts in I3C Controller 5.8.6.5. Overview of Master Role in I3C 5.8.6.6. Overview of Slave Role in I3C
5.8.6.5. Overview of Master Role in I3C x
5.8.6.5.1. Dynamic Address Assignment (DAA) 5.8.6.5.2. In-Band Interrupt (IBI) Detection and Handling 5.8.6.5.3. I3C Slave Interrupt Request (SIR) 5.8.6.5.4. Disabling I3C Master 5.8.6.5.5. Aborting Transfers of I3C Master 5.8.6.5.6. I3C Master Request (MR) 5.8.6.5.7. Master Command Data Structures 5.8.6.5.8. Response Data Structure 5.8.6.5.9. Operation Modes of I3C Controller 5.8.6.5.10. SCL Generation and Timings Based on Bus Configuration 5.8.6.5.11. Derivation of I3C/I2C Timing Parameters from Timing Registers 5.8.6.5.12. Error Detection 5.8.6.5.13. Defining Byte Support 5.8.6.5.14. Broadcast CCCs in I2C Speed 5.8.6.5.15. BUS RESET Generation DMA Controller Interface
5.8.6.5.1. Dynamic Address Assignment (DAA) x
5.8.6.5.1.1. SETDASA (Format 1: Primary) 5.8.6.5.1.2. SETDASA (Format 2: Point-to-Point) 5.8.6.5.1.3. ENTDAA 5.8.6.5.1.4. SETAASA
5.8.6.5.3. I3C Slave Interrupt Request (SIR) x
5.8.6.5.3.1. SIR Response Control
5.8.6.5.6. I3C Master Request (MR) x
5.8.6.5.6.1. MR Response Control
5.8.6.5.7. Master Command Data Structures x
5.8.6.5.7.1. Transfer Command Data Structure 5.8.6.5.7.2. Transfer Argument Data Structure 5.8.6.5.7.3. Short Data Argument Data Structure 5.8.6.5.7.4. Address Assignment Command Data Structure
5.8.6.5.9. Operation Modes of I3C Controller x
5.8.6.5.9.1. Single Data Rate (SDR) Transfers in Master Mode 5.8.6.5.9.2. Broadcast CCC Write Transfers 5.8.6.5.9.3. Directed Write and Read Transfers 5.8.6.5.9.4. Directed CCC Transfer Targeted to Multiple Slaves 5.8.6.5.9.5. I3C Private Write or Read Transfers 5.8.6.5.9.6. I2C Private Write or Read Transfers 5.8.6.5.9.7. Implication of TX-FIFO Empty and RX-FIFO Full Conditions 5.8.6.5.9.8. Implication of TOC and ROC Bit Settings for SDR Transfers
5.8.6.5.12. Error Detection x
5.8.6.5.12.1. Detecting Error Type in the Processed Commands 5.8.6.5.12.2. SDR Error Detection and Recovery Methods
5.8.6.6. Overview of Slave Role in I3C x
5.8.6.6.1. Description of the Slave Role in I3C 5.8.6.6.2. I3C versus I2C Role Selection 5.8.6.6.3. Slave Role Related Registers 5.8.6.6.4. Handling Address Assignment 5.8.6.6.5. CCC Transfers with I3C Slave 5.8.6.6.6. Private Data Transfers 5.8.6.6.7. Handling Private Transmit (Master Read) Transfers 5.8.6.6.8. Slave Interrupt Request Generation 5.8.6.6.9. Master Request Generation 5.8.6.6.10. Disabling I3C Slave 5.8.6.6.11. Data Structure in I3C Slave
5.8.6.6.6. Private Data Transfers x
5.8.6.6.6.1. Overview of Private Data Transfers
5.8.6.6.11. Data Structure in I3C Slave x
5.8.6.6.11.1. Transmit Command Data Structure 5.8.6.6.11.2. Response Data Structure
5.8.7. I3C Controller Programming Model x
5.8.7.1. Initializing Common Registers 5.8.7.2. Initializing Master Registers 5.8.7.3. Enabling the Controller 5.8.7.4. Master Mode Operation 5.8.7.5. Initializing Slave Registers 5.8.7.6. Slave Mode Operation 5.8.7.7. DMA Controller Operation
5.8.7.1. Initializing Common Registers x
5.8.7.1.1. Programming Threshold Control Registers 5.8.7.1.2. Programming Interrupt Related Registers
5.8.7.2. Initializing Master Registers x
5.8.7.2.1. Programming DEVICE_ADDR Register 5.8.7.2.2. Programming Timing Registers
5.8.7.4. Master Mode Operation x
5.8.7.4.1. Slave Address Assignment 5.8.7.4.2. Receiving IBI (All types) 5.8.7.4.3. CCC Read/Write Transfers 5.8.7.4.4. Private Read/Write Transfers 5.8.7.4.5. Programming Flow to Prepare the Controller to Switch to Master Mode
5.8.7.4.1. Slave Address Assignment x
5.8.7.4.1.1. ENTDAA Transfer 5.8.7.4.1.2. Issue SETDASA CCC Command
5.8.7.4.3. CCC Read/Write Transfers x
5.8.7.4.3.1. Broadcast CCC Transfer in Master Mode 5.8.7.4.3.2. Directed CCC Transfer in Master Mode
5.8.7.5. Initializing Slave Registers x
5.8.7.5.1. Programming Interrupt Related Registers
5.8.7.6. Slave Mode Operation x
5.8.7.6.1. Private Receive (Master Write) Transfers in Slave Mode 5.8.7.6.2. Private Transmit (Master Read) Transfers in Slave Mode 5.8.7.6.3. Programming Flow for Generating Slave Interrupt Request 5.8.7.6.4. Programming Flow for Generating Master Request 5.8.7.6.5. Programming Flow to Prepare the Controller to Switch to Master Mode 5.8.7.6.6. Command Pipeline and Aggregation of Response Queue Threshold Interrupt 5.8.7.6.7. Error Recovery Flow 5.8.7.6.8. CCC Updated Interrupt Flow 5.8.7.6.9. Flow for Disable and TX/RX/CMD/Response Queue Reset
5.8.7.6.7. Error Recovery Flow x
5.8.7.6.7.1. S0-S5 Error Handling
5.8.9. I3C Controller Design Guidelines and Examples x
5.8.9.1. Guidelines for External SDA and SCL Signals via HPS I/O in the Board Design
5.9. I2C Controller x
5.9.1. I2C Controller Differences Among Intel SoC Device Families 5.9.2. I2C Controller Use Cases 5.9.3. I2C Controller Features 5.9.4. I2C Controller System Integration 5.9.5. I2C Controller Signal Description 5.9.6. I2C Controller Functional Description 5.9.7. I2C Controller Programming Model 5.9.8. I2C Controller Address Map and Register Definitions 5.9.9. I2C Controller Design Guidelines and Examples
5.9.6. I2C Controller Functional Description x
5.9.6.1. Feature Usage 5.9.6.2. Behavior 5.9.6.3. Protocol Details 5.9.6.4. Multiple Master Arbitration 5.9.6.5. Clock Frequency Configuration 5.9.6.6. SDA Hold Time 5.9.6.7. DMA Controller Interface 5.9.6.8. Clocks 5.9.6.9. Resets
5.9.6.2. Behavior x
5.9.6.2.1. START and STOP Generation 5.9.6.2.2. Combined Formats
5.9.6.3. Protocol Details x
5.9.6.3.1. START and STOP Conditions 5.9.6.3.2. Addressing Slave Protocol 5.9.6.3.3. Transmitting and Receiving Protocol 5.9.6.3.4. START BYTE Transfer Protocol
5.9.6.4. Multiple Master Arbitration x
5.9.6.4.1. Clock Synchronization
5.9.6.5. Clock Frequency Configuration x
5.9.6.5.1. Minimum High and Low Counts
5.9.6.5.1. Minimum High and Low Counts x
5.9.6.5.1.1. Calculating High and Low Counts
5.9.6.9. Resets x
5.9.6.9.1. Taking the I2C Controller Out of Reset
5.9.7. I2C Controller Programming Model x
5.9.7.1. Slave Mode Operation 5.9.7.2. Master Mode Operation 5.9.7.3. Disabling the I2C Controller 5.9.7.4. Abort Transfer 5.9.7.5. DMA Controller Operation
5.9.7.1. Slave Mode Operation x
5.9.7.1.1. Initial Configuration 5.9.7.1.2. Slave-Transmitter Operation for a Single Byte 5.9.7.1.3. Slave-Receiver Operation for a Single Byte 5.9.7.1.4. Slave-Transfer Operation for Bulk Transfers 5.9.7.1.5. Slave Programming Model
5.9.7.2. Master Mode Operation x
5.9.7.2.1. Initial Configuration 5.9.7.2.2. Dynamic IC_TAR or IC_10BITADDR_MASTER Update 5.9.7.2.3. Master Transmit and Master Receive 5.9.7.2.4. Master Programming Model
5.9.7.5. DMA Controller Operation x
5.9.7.5.1. Transmit FIFO Underflow 5.9.7.5.2. Transmit Watermark Level 5.9.7.5.3. Transmit FIFO Overflow 5.9.7.5.4. Receive FIFO Overflow 5.9.7.5.5. Receive Watermark Level 5.9.7.5.6. Receive FIFO Underflow
5.9.9. I2C Controller Design Guidelines and Examples x
5.9.9.1. I2C Interface Design Guidelines
5.10. SPI Controller x
5.10.1. SPI Controller Differences Among Intel SoC Device Families 5.10.2. SPI Controller Use Cases 5.10.3. SPI Controller Features 5.10.4. SPI Controller System Integration 5.10.5. SPI Controller Signal Description 5.10.6. SPI Controller Functional Description 5.10.7. SPI Controller Programming Model 5.10.8. SPI Controller Address Map and Register Definitions
5.10.5. SPI Controller Signal Description x
5.10.5.1. Interface to HPS I/O 5.10.5.2. FPGA Routing
5.10.6. SPI Controller Functional Description x
5.10.6.1. Protocol Details and Standards Compliance 5.10.6.2. Overview 5.10.6.3. Serial Bit-Rate Clocks 5.10.6.4. Transmit and Receive FIFO Buffers 5.10.6.5. SPI Interrupts 5.10.6.6. Transfer Modes 5.10.6.7. SPI Master 5.10.6.8. SPI Slave 5.10.6.9. Partner Connection Interfaces 5.10.6.10. DMA Controller Interface 5.10.6.11. Slave Interface 5.10.6.12. Clocks and Resets
5.10.6.3. Serial Bit-Rate Clocks x
5.10.6.3.1. SPI Master Bit-Rate Clock 5.10.6.3.2. SPI Slave Bit-Rate Clock
5.10.6.6. Transfer Modes x
5.10.6.6.1. Transmit and Receive 5.10.6.6.2. Transmit Only 5.10.6.6.3. Receive Only 5.10.6.6.4. EEPROM Read
5.10.6.7. SPI Master x
5.10.6.7.1. Glue Logic for Master Port ss_in_n 5.10.6.7.2. Multi-Master System 5.10.6.7.3. RXD Sample Delay 5.10.6.7.4. Data Transfers 5.10.6.7.5. Master SPI and SSP Serial Transfers 5.10.6.7.6. Master Microwire Serial Transfers
5.10.6.8. SPI Slave x
5.10.6.8.1. Slave SPI and SSP Serial Transfers 5.10.6.8.2. Serial Transfers
5.10.6.9. Partner Connection Interfaces x
5.10.6.9.1. Motorola SPI Protocol 5.10.6.9.2. Texas Instruments Synchronous Serial Protocol (SSP) 5.10.6.9.3. National Semiconductor Microwire Protocol
5.10.6.11. Slave Interface x
5.10.6.11.1. Control and Status Register Access 5.10.6.11.2. Data Register Access
5.10.6.12. Clocks and Resets x
5.10.6.12.1. Clock Gating 5.10.6.12.2. Taking the SPI Controller Out of Reset
5.10.7. SPI Controller Programming Model x
5.10.7.1. Master SPI and SSP Serial Transfers 5.10.7.2. Master Microwire Serial Transfers 5.10.7.3. Slave SPI and SSP Serial Transfers 5.10.7.4. Slave Microwire Serial Transfers 5.10.7.5. Software Control for Slave Selection 5.10.7.6. DMA Controller Operation
5.10.7.5. Software Control for Slave Selection x
5.10.7.5.1. Example: Slave Selection Software Flow for SPI Master 5.10.7.5.2. Example: Slave Selection Software Flow for SPI Slave
5.10.7.6. DMA Controller Operation x
5.10.7.6.1. Transmit FIFO Buffer Underflow 5.10.7.6.2. Transmit FIFO Watermark 5.10.7.6.3. Transmit FIFO Buffer Overflow 5.10.7.6.4. Receive FIFO Buffer Overflow 5.10.7.6.5. Choosing Receive Watermark Level 5.10.7.6.6. Receive FIFO Buffer Underflow
5.10.7.6.2. Transmit FIFO Watermark x
5.10.7.6.2.1. Example 1: Transmit FIFO Watermark Level = 64 5.10.7.6.2.2. Example 2: Transmit FIFO Watermark Level = 192
5.11. Timers x
5.11.1. Timers Differences Among Intel SoC Device Families 5.11.2. Timers Use Cases 5.11.3. Timers Features 5.11.4. Timers System Integration 5.11.5. Timers Functional Description 5.11.6. Timers Programming Model 5.11.7. Timers Address Map and Register Definitions
5.11.5. Timers Functional Description x
5.11.5.1. Clocks 5.11.5.2. Resets 5.11.5.3. Interrupts
5.11.6. Timers Programming Model x
5.11.6.1. Initialization 5.11.6.2. Enabling the Timers 5.11.6.3. Disabling the Timers 5.11.6.4. Loading the Timers Countdown Value 5.11.6.5. Timers Servicing Interrupts
5.11.6.5. Timers Servicing Interrupts x
5.11.6.5.1. Clearing the Interrupt 5.11.6.5.2. Checking the Interrupt Status 5.11.6.5.3. Masking the Interrupt
5.12. Watchdog Timers x
5.12.1. Watchdog Timers Differences Among Intel SoC Device Families 5.12.2. Watchdog Timers Use Cases 5.12.3. Watchdog Timers Features 5.12.4. Watchdog Timers System Integration 5.12.5. Watchdog Timers Functional Description 5.12.6. Watchdog Timers Programming Model 5.12.7. Watchdog Timers Address Map and Register Definitions
5.12.5. Watchdog Timers Functional Description x
5.12.5.1. Watchdog Timers Counter 5.12.5.2. Watchdog Timers Pause Mode 5.12.5.3. Watchdog Timers Clocks 5.12.5.4. Watchdog Timers Resets
5.12.6. Watchdog Timers Programming Model x
5.12.6.1. Setting the Timeout Period Values 5.12.6.2. Selecting the Output Response Mode 5.12.6.3. Enabling and Initially Starting a Watchdog Timers 5.12.6.4. Reloading a Watchdog Counter 5.12.6.5. Pausing a Watchdog Timers 5.12.6.6. Disabling and Stopping a Watchdog Timers 5.12.6.7. Watchdog Timers State Machine
5.13. UART Controller x
5.13.1. UART Controller Differences Among Intel SoC Device Families 5.13.2. UART Controller Use Cases 5.13.3. UART Controller Features 5.13.4. UART Controller System Integration 5.13.5. UART Controller Signal Description 5.13.6. UART Controller Functional Description 5.13.7. UART Controller Address Map and Register Definitions 5.13.8. UART Controller Design Guidelines and Example
5.13.5. UART Controller Signal Description x
5.13.5.1. HPS I/O Pins 5.13.5.2. FPGA Routing
5.13.6. UART Controller Functional Description x
5.13.6.1. FIFO Buffer Support 5.13.6.2. UART Serial Protocol 5.13.6.3. Automatic Flow Control 5.13.6.4. Clocks 5.13.6.5. Resets 5.13.6.6. UART Controller Interrupts 5.13.6.7. UART Controller DMA Controller Operation
5.13.6.7. UART Controller DMA Controller Operation x
5.13.6.7.1. Transmit FIFO Underflow 5.13.6.7.2. Transmit Watermark Level 5.13.6.7.3. Transmit FIFO Overflow 5.13.6.7.4. Receive FIFO Overflow 5.13.6.7.5. Receive Watermark Level 5.13.6.7.6. Receive FIFO Underflow
5.14. General-Purpose I/O Interface (GPIO) x
5.14.1. GPIO Differences Among Intel SoC Device Families 5.14.2. GPIO Use Cases 5.14.3. GPIO Features 5.14.4. GPIO System Integration 5.14.5. GPIO Functional Description 5.14.6. GPIO Programming Model 5.14.7. GPIO Address Map and Register Definitions
5.14.5. GPIO Functional Description x
5.14.5.1. Interrupts 5.14.5.2. Debounce Operation 5.14.5.3. Pin Directions 5.14.5.4. Taking the GPIO Interface Out of Reset
5.15. Hard Processor System I/O Pin Multiplexing x
5.15.1. I/O Pin Multiplexing Differences Among Intel SoC Device Families 5.15.2. I/O Pin Multiplexing Use Cases 5.15.3. I/O Pin Multiplexing Features 5.15.4. I/O Pin Multiplexing System Integration 5.15.5. I/O Pin Multiplexing Functional Description 5.15.6. I/O Pin Multiplexing Address Map and Register Definitions 5.15.7. I/O Pin Multiplexing Design Guidelines and Examples
5.15.5. I/O Pin Multiplexing Functional Description x
5.15.5.1. I/O Pins 5.15.5.2. FPGA Access 5.15.5.3. I/O Control Registers
5.15.5.3. I/O Control Registers x
5.15.5.3.1. Dedicated Pin MUX Registers 5.15.5.3.2. Dedicated Configuration Registers 5.15.5.3.3. FPGA Access MUX Registers 5.15.5.3.4. HPS JTAG Pin MUX Register
5.15.7. I/O Pin Multiplexing Design Guidelines and Examples x
5.15.7.1. Boundary Scan for HPS 5.15.7.2. HPS I/O Design Considerations
6. System Manager x
6.1. System Manager Differences Among Intel SoC Device Families 6.2. System Manager Use Cases 6.3. System Manager Features 6.4. System Manager System Integration 6.5. System Manager Address Map and Register Definitions 6.6. System Manager Revision History
6.4. System Manager System Integration x
6.4.1. Additional Module Control 6.4.2. FPGA Interface Enables 6.4.3. ECC and Parity Control 6.4.4. Preloader Handoff Information 6.4.5. Clocks 6.4.6. Resets
6.4.1. Additional Module Control x
6.4.1.1. DMA Controller 6.4.1.2. NAND Flash Controller 6.4.1.3. EMAC 6.4.1.4. USB 2.0 OTG Controller 6.4.1.5. USB 3.1 Controller 6.4.1.6. NOC Registers 6.4.1.7. Boot Scratch Space 6.4.1.8. I3C Controller 6.4.1.9. SD/eMMC Controller 6.4.1.10. GPIO Interconnect Between the HPS and FPGA 6.4.1.11. Watchdog Timer
7. Clock Manager x
7.1. Clock Manager Differences Among Intel SoC Device Families 7.2. Clock Manager Use Cases 7.3. Clock Manager Features 7.4. Clock Manager System Integration 7.5. Clock Manager Signal Description 7.6. Clock Manager Functional Description 7.7. Clock Manager Programming Model 7.8. Clock Manager Address Map and Register Definitions 7.9. Clock Manager Design Guidelines and Examples
7.2. Clock Manager Use Cases x
7.2.1. A76 Core Power and Performance Trade-off 7.2.2. A55 Core Power and Performance Trade-off 7.2.3. DSU Power and Performance Trade-off 7.2.4. Peripheral Clock Generation 7.2.5. Peripheral Power Optimization 7.2.6. Clock Tree Clock Sources 7.2.7. Boot Clock 7.2.8. Power-on-reset 7.2.9. Boot Mode 7.2.10. Disable Clocks Before Reset Assertion 7.2.11. PLL Configuration using JTAG
7.4. Clock Manager System Integration x
7.4.1. Top Level of the Clock Groups 7.4.2. Clock Manager Block Diagram
7.5. Clock Manager Signal Description x
7.5.1. Hardware-Managed Clocks 7.5.2. Software-Managed Clocks
7.6. Clock Manager Functional Description x
7.6.1. PLL Wrapper 7.6.2. MPU/DSU and APS/CCU Clock Groups 7.6.3. PSS Clock Group 7.6.4. MPFE Clock Group 7.6.5. EMAC and XGMAC Clock Group 7.6.6. USB31 Clock Group 7.6.7. SD/eMMC, NAND, and SoftPHY/ComboPHY 7.6.8. H2F User Clock Group 7.6.9. F2H User Clock Group 7.6.10. GPIO Debounce Clock Group 7.6.11. CoreSight Clocks 7.6.12. PSI Clock Group (to the SDM)
7.6.3. PSS Clock Group x
7.6.3.1. USB2OTG Clock Group
7.6.5. EMAC and XGMAC Clock Group x
7.6.5.1. EMAC Clocks 7.6.5.2. XGMAC Clocks
7.7. Clock Manager Programming Model x
7.7.1. Example Configuration of Registers for Default Operation (640 MHz CPU) 7.7.2. Example Configuration of Registers for Power Optimized (1000 MHz CPU) 7.7.3. Example Configuration of Registers for Performance Optimized (1800 MHz CPU) 7.7.4. Example Configuration of Registers for Power Optimized (1200 MHz CPU) 7.7.5. Summary Table of Registers Used to Program Clocks
8. Reset Manager x
8.1. Reset Manager Differences Among Intel SoC Device Families 8.2. Reset Manager Use Cases 8.3. Reset Manager Features 8.4. Reset Manager System Integration 8.5. Reset Manager Signal Description 8.6. Reset Manager Functional Description 8.7. Reset Manager Programming Model 8.8. Reset Manager Address Map and Register Definitions
8.5. Reset Manager Signal Description x
8.5.1. HPS Reset Domains 8.5.2. HPS Reset Domain to Signal Mapping 8.5.3. HPS Reset Priority
8.6. Reset Manager Functional Description x
8.6.1. System Reset High Level Flow 8.6.2. Hardware Reset Sequences 8.6.3. Software Reset Sequences
8.6.2. Hardware Reset Sequences x
8.6.2.1. POR De-assertion Sequence 8.6.2.2. Reset De-assertion Sequence 8.6.2.3. HPS Idle Sequence 8.6.2.4. Reset Assertion Sequence 8.6.2.5. Wait for Reset Requests to De-assert Sequence
8.6.3. Software Reset Sequences x
8.6.3.1. Normal Operation 8.6.3.2. Cold and Warm Reset Sequence 8.6.3.3. Debug Reset Sequence
8.7. Reset Manager Programming Model x
8.7.1. H2F Bridge Reset Sequence 8.7.2. LWH2F Bridge Reset Sequence 8.7.3. F2H Bridge Reset Sequence 8.7.4. F2SDRAM Bridge Reset Sequence 8.7.5. HPS_COLD_nRESET Pin Function
8.7.5. HPS_COLD_nRESET Pin Function x
8.7.5.1. FPGA Boot First 8.7.5.2. HPS Boot First 8.7.5.3. HPS Pin-triggered Cold Reset 8.7.5.4. HPS Mailbox-triggered Cold Reset
9. Power Management x
9.1. Power Management Differences Among Intel SoC Device Families 9.2. Power Management System Integration 9.3. Power Management Functional Description 9.4. Power Management Design Guidelines and Examples
9.3. Power Management Functional Description x
9.3.1. DSU L3 Cache Power Gating 9.3.2. CPU Core Power Gating 9.3.3. PSS Partition Power Management
10. Address Map x
10.1. Address Space Introduction 10.2. Total Address Spaces 10.3. MPU Address Space 10.4. NOC: Level 3 and Level 4 Address Space 10.5. FPGA Slaves Address Space 10.6. Lightweight FPGA Slaves Address Space 10.7. FPGA-to-HPS Address Space 10.8. FPGA-to-SDRAM Address Space
10.2. Total Address Spaces x
10.2.1. Total Address Map Graphical 10.2.2. Total Address Map Tabular 10.2.3. Total Address Map for F2H and F2SDRAM
11. Bridges x
11.1. Bridges Differences Among Intel SoC Device Families 11.2. Bridges Use Cases 11.3. Bridges Features 11.4. Bridges System Integration 11.5. Bridges Functional Description 11.6. Bridges Clocks and Resets 11.7. Bridges Address Map and Register Definitions 11.8. Bridges Design Guidelines and Examples
11.2. Bridges Use Cases x
11.2.1. FPGA-to-HPS Bridge 11.2.2. HPS-to-FPGA 11.2.3. Lightweight HPS-to-FPGA 11.2.4. FPGA-to-SDRAM
11.2.1. FPGA-to-HPS Bridge x
11.2.1.1. FPGA-to-HPS Initialization and Shutdown Procedure
11.5. Bridges Functional Description x
11.5.1. FPGA-to-HPS Bridge 11.5.2. HPS-to-FPGA Bridge 11.5.3. Lightweight HPS-to-FPGA Bridge 11.5.4. FPGA-to-SDRAM Bridge
11.5.4. FPGA-to-SDRAM Bridge x
11.5.4.1. Transaction Buffer Unit Interface
11.6. Bridges Clocks and Resets x
11.6.1. FPGA-to-HPS Bridge Clocks and Resets 11.6.2. HPS-to-FPGA Bridge Clocks and Resets 11.6.3. Lightweight HPS-to-FPGA Bridge Clocks and Resets 11.6.4. FPGA-to-SDRAM Clocks and Resets
11.8. Bridges Design Guidelines and Examples x
11.8.1. Recommended Starting Point for Interface Designs 11.8.2. Information on How to Configure and Use the Bridges 11.8.3. Bridges Example Transactions
11.8.3. Bridges Example Transactions x
11.8.3.1. FPGA-to-SDRAM Direct (Cache Non-Allocate) 11.8.3.2. FPGA-to-HPS CCU to Memory (Cache Non-Allocate) 11.8.3.3. FPGA-to-HPS CCU to Memory (Cache-Allocate) 11.8.3.4. FPGA-to-HPS CCU to Peripherals (Device Non-Bufferable) 11.8.3.5. FPGA-to-HPS Example Transactions Summary
12. Interfaces x
12.1. HPS Mailbox 12.2. MPFE and MPFE-lite 12.3. EMAC GMII through FPGA Fabric
12.1. HPS Mailbox x
12.1.1. HPS Mailbox Differences Among Intel SoC Device Families 12.1.2. HPS Mailbox Features 12.1.3. Accessing HPS Mailbox Services 12.1.4. HPS Mailbox System Integration 12.1.5. HPS Mailbox Address Map and Register Definitions
12.2. MPFE and MPFE-lite x
12.2.1. MPFE and MPFE-lite Terminology 12.2.2. MPFE and MPFE-lite Differences Among Intel SoC Families 12.2.3. MPFE and MPFE-lite Use Cases 12.2.4. MPFE and MPFE-lite Features 12.2.5. MPFE and MPFE-lite System Integration 12.2.6. MPFE and MPFE-lite Functional Description 12.2.7. MPFE and MPFE-lite Address Map and Register Definitions
12.2.3. MPFE and MPFE-lite Use Cases x
12.2.3.1. Fabric Bypass 12.2.3.2. One 16-bit SDRAM channel 12.2.3.3. One 32-bit SDRAM channel 12.2.3.4. Two 16-bit SDRAM channels utilizing a single IOBank 12.2.3.5. Two 16-bit or two 32-bit SDRAM channels utilizing two IOBank 12.2.3.6. Four 16-bit SDRAM channels utilizing two IOBank 12.2.3.7. Supports up to 512GB of memory 12.2.3.8. Supports sideband ECC on DDR4/5 12.2.3.9. Supports inband ECC on LPDDR4/5
12.2.5. MPFE and MPFE-lite System Integration x
12.2.5.1. Block Diagram (High Level) 12.2.5.2. IOBank Introduction
12.2.6. MPFE and MPFE-lite Functional Description x
12.2.6.1. Block Diagram 12.2.6.2. Interfaces 12.2.6.3. AxUSER Bit Connectivity 12.2.6.4. Fabric Bypass 12.2.6.5. FPGA-to-SDRAM bridge 12.2.6.6. FPGA-to-HPS bridge 12.2.6.7. MPFE NoC 12.2.6.8. MPFE-lite / MPFE-lite NoC 12.2.6.9. Address Gap Glue Logic 12.2.6.10. Resets Circuitry 12.2.6.11. Clocks Circuitry 12.2.6.12. Preserving SDRAM contents
12.3. EMAC GMII through FPGA Fabric x
12.3.1. GMII to RGMII through RGMII adapter via FPGA HVIOs 12.3.2. GMII to SGMII+ through Multi-Rate Ethernet PHY Adapter via FPGA IOs
12.3.1. GMII to RGMII through RGMII adapter via FPGA HVIOs x
12.3.1.1. Use Cases 12.3.1.2. System Integration 12.3.1.3. Architecture 12.3.1.4. Programming Model 12.3.1.5. RGMII Design Guidelines
12.3.1.3. Architecture x
12.3.1.3.1. HPS GMII to RGMII Adapter Intel FPGA IP 12.3.1.3.2. MDIO Management Interface 12.3.1.3.3. Timestamp Interface 12.3.1.3.4. RGMII HVIO Pin Assignment
12.3.1.5. RGMII Design Guidelines x
12.3.1.5.1. Utilize FPGA Programmable IOE Delay Feature 12.3.1.5.2. Configure External PHY RGMII-Internal Delay (RGMII-ID) 12.3.1.5.3. Introduce Board Trace Delay
13. System Interconnect and Firewalls x
13.1. System Interconnect and Firewalls Differences Among Intel SoC Device Families 13.2. System Interconnect and Firewalls Features 13.3. System Interconnect and Firewalls System Integration 13.4. System Interconnect and Firewalls Functional Description 13.5. System Interconnect and Firewalls Address Map and Register Definitions
13.4. System Interconnect and Firewalls Functional Description x
13.4.1. Initiator and Target Connectivity 13.4.2. Firewall and Security 13.4.3. Transaction Privilege 13.4.4. Arbitration and Quality-of-Service 13.4.5. Observation Network 13.4.6. System Interconnect Clocks 13.4.7. System Interconnect Resets
13.4.2. Firewall and Security x
13.4.2.1. Initiator Firewall and Security 13.4.2.2. Target Firewall and Security 13.4.2.3. F2H Bridge Firewall 13.4.2.4. MPFE Firewalls 13.4.2.5. Other Firewalls
13.4.2.4. MPFE Firewalls x
13.4.2.4.1. DDR Firewalls 13.4.2.4.2. CSR Firewall 13.4.2.4.3. F2SDRAM AxUSER Firewall
13.4.4. Arbitration and Quality-of-Service x
13.4.4.1. Priority Levels 13.4.4.2. Urgency and Pressure Signals 13.4.4.3. Passing QOS across NoCs 13.4.4.4. QoS Generators
13.4.5. Observation Network x
13.4.5.1. Interconnect Probes Generators 13.4.5.2. Packet Tracing, Profiling, Statistics, Alarms, and Error Logs
14. Error Checking and Correction Controller x
14.1. ECC Differences Among Intel SoC Device Families 14.2. ECC Controller Use Cases 14.3. ECC Controller Features 14.4. ECC Supported Memories 14.5. ECC Controller System Integration 14.6. ECC Controller Functional Description 14.7. ECC Controller Address Map and Register Definitions
14.6. ECC Controller Functional Description x
14.6.1. ECC Structure 14.6.2. Memory Data Initialization 14.6.3. Indirect Memory Access 14.6.4. Error Checking and Correction Algorithm 14.6.5. Error Logging 14.6.6. ECC Controller Interrupts 14.6.7. ECC Controller Initialization and Configuration 14.6.8. ECC Controller Clocks 14.6.9. ECC Controller Reset
14.6.1. ECC Structure x
14.6.1.1. RAM and ECC Memory Organization Example
14.6.3. Indirect Memory Access x
14.6.3.1. Watchdog Timer 14.6.3.2. Data Correction 14.6.3.3. Error Injection 14.6.3.4. Memory Testing
14.6.3.4. Memory Testing x
14.6.3.4.1. Register Interface Tests
14.6.3.4.1. Register Interface Tests x
14.6.3.4.1.1. Single-Bit Error Test for Word-Writeable Memories 14.6.3.4.1.2. Double-Bit Error Test
14.6.5. Error Logging x
14.6.5.1. Recent Error Address Registers 14.6.5.2. Single-Bit Error Occurrence 14.6.5.3. Single-Bit Error Look-Up Table
14.6.6. ECC Controller Interrupts x
14.6.6.1. Single-Bit Error Interrupts 14.6.6.2. Double-Bit Error Interrupt 14.6.6.3. Interrupt Testing 14.6.6.4. Interrupt Testing
14.6.6.1. Single-Bit Error Interrupts x
14.6.6.1.1. All Single-Bit Error Interrupt 14.6.6.1.2. LUT Overflow Interrupt 14.6.6.1.3. Counter Match Interrupt
15. CoreSight Debug and Trace x
15.1. CoreSight* Debug and Trace Differences Among Intel SoC Device Families 15.2. CoreSight Debug and Trace Use Cases 15.3. CoreSight Debug and Trace Features 15.4. CoreSight* Debug and Trace System Integration 15.5. CoreSight Debug and Trace Functional Description 15.6. CoreSight Debug and Trace Programming Model 15.7. CoreSight* Debug and Trace Address Map and Register Definitions
15.2. CoreSight Debug and Trace Use Cases x
15.2.1. CPU Static Debug 15.2.2. CPU Trace using Embedded Trace Macrocell
15.3. CoreSight Debug and Trace Features x
15.3.1. Debug 15.3.2. Trace
15.3.1. Debug x
15.3.1.1. CPU Performance Events 15.3.1.2. Cross Triggers 15.3.1.3. Fabric Coresight APB
15.3.2. Trace x
15.3.2.1. System Trace Macrocell 15.3.2.2. NoC Trace 15.3.2.3. Fabric Coresight Trace
15.3.2.3. Fabric Coresight Trace x
15.3.2.3.1. Fabric Trace using CoreSight Trace Network 15.3.2.3.2. Timestamp Correlation using ATB SYNCREQ 15.3.2.3.3. Timestamp Correlation using STM HWEVENT
15.5. CoreSight Debug and Trace Functional Description x
15.5.1. Debug APB 15.5.2. Trace Subsystem 15.5.3. Cross Triggers 15.5.4. Timestamp 15.5.5. Embedded Cross Trigger System 15.5.6. HPS Debug APB Interface 15.5.7. FPGA Interface 15.5.8. Interrupts
15.5.1. Debug APB x
15.5.1.1. ROM Tables & Topology Detection 15.5.1.2. DAP SWJ-DP JTAG I/O Connectivity 15.5.1.3. DAP SWJ-DP Debug Clock Enable Request 15.5.1.4. Debug Reset 15.5.1.5. DAP SWJ-DP TargetID 15.5.1.6. DAP TDO Output to SDM in Daisy Chain Mode
15.5.1.4. Debug Reset x
15.5.1.4.1. Debug Reset Request via Reset Manager CSR 15.5.1.4.2. Debug Reset Request via DAP SWJ-DP 15.5.1.4.3. Debug Reset Limitation
15.5.2. Trace Subsystem x
15.5.2.1. Embedded Trace Macrocell (ETM) 15.5.2.2. System Trace Macrocell (STM) 15.5.2.3. PSS NOC and MPFE NOC 15.5.2.4. AMBA* Trace Bus (ATB) 15.5.2.5. Trace Port Interface Unit (TPIU) 15.5.2.6. Embedded Trace FIFO (ETF) 15.5.2.7. Embedded Trace Router (ETR) 15.5.2.8. ATB IDs 15.5.2.9. NOC Trace Observability 15.5.2.10. STM HWEVENT Connectivity
15.5.2.9. NOC Trace Observability x
15.5.2.9.1. Error Probes 15.5.2.9.2. Packet Probes 15.5.2.9.3. Transaction Probes
15.5.3. Cross Triggers x
15.5.3.1. CTI-GT 15.5.3.2. CTI-NOC 15.5.3.3. CTI-5 15.5.3.4. CTI-FPGA 15.5.3.5. CTI-MPU
15.5.4. Timestamp x
15.5.4.1. Timestamp Interpolater
15.5.5. Embedded Cross Trigger System x
15.5.5.1. Cross Trigger Interface 15.5.5.2. Cross Trigger Matrix
15.5.7. FPGA Interface x
15.5.7.1. DAP 15.5.7.2. System Trace Macrocell (STM) 15.5.7.3. CTI-FPGA 15.5.7.4. Trace Port Interface Unit (TPIU) 15.5.7.5. CoreSight* Debug and Trace Clocks 15.5.7.6. CoreSight* Debug and Trace Resets
15.6. CoreSight Debug and Trace Programming Model x
15.6.1. CoreSight Component Address 15.6.2. CTI Trigger Connections to Outside the Debug System 15.6.3. Configuring Embedded Cross-Trigger Connections
15.6.2. CTI Trigger Connections to Outside the Debug System x
15.6.2.1. CTI 15.6.2.2. FPGA-CTI 15.6.2.3. L3-CTI
15.6.3. Configuring Embedded Cross-Trigger Connections x
15.6.3.1. Configuring Trigger Input 0 15.6.3.2. Triggering a Flush of Trace Data to the TPIU 15.6.3.3. Triggering an STM Message 15.6.3.4. Triggering a Breakpoint on CPU 1
A. Appendix x
A.1. Booting and Configuration A.2. HPS Use of SDM QSPI Controller A.3. Security A.4. Operational Status of the HPS to the FPGA Logic
A.1. Booting and Configuration x
A.1.1. Booting and Configuration Features A.1.2. Booting and Configuration FPGA Configuration First Mode Overview A.1.3. Booting and Configuration HPS Boot First Mode Overview A.1.4. Booting and Configuration Device Response to External Configuration and Reset Events
A.2. HPS Use of SDM QSPI Controller x
A.2.1. HPS Use of SDM QSPI Controller Differences Among Intel SoC Device Families A.2.2. HPS Use of SDM QSPI Controller Use Cases A.2.3. HPS Use of SDM QSPI Controller Features A.2.4. HPS Use of SDM QSPI Controller System Integration A.2.5. HPS Use of SDM QSPI Controller Signal Description A.2.6. HPS Use of SDM QSPI Controller Functional Description A.2.7. HPS Use of SDM QSPI Controller Programming Model A.2.8. HPS Use of SDM QSPI Controller Address Map and Register Definitions A.2.9. HPS Use of SDM QSPI Controller Design Guidelines and Examples
A.2.6. HPS Use of SDM QSPI Controller Functional Description x
A.2.6.1. Data Target Interface A.2.6.2. Register Target Interface A.2.6.3. Local Memory Buffer A.2.6.4. Arbitration between Direct/Indirect Access Controller and STIG A.2.6.5. Configuring the Flash Device A.2.6.6. Write Protection A.2.6.7. Data Target Sequential Access Detection A.2.6.8. Clocks A.2.6.9. Resets A.2.6.10. Interrupts
A.2.6.1. Data Target Interface x
A.2.6.1.1. Direct Access Mode A.2.6.1.2. Indirect Access Mode
A.2.6.1.1. Direct Access Mode x
A.2.6.1.1.1. Data Target Remapping Example A.2.6.1.1.2. AHB
A.2.6.1.2. Indirect Access Mode x
A.2.6.1.2.1. Indirect Read Operation A.2.6.1.2.2. Indirect Write Operation A.2.6.1.2.3. Consecutive Reads and Writes
A.2.6.2. Register Target Interface x
A.2.6.2.1. STIG Operation
A.2.7. HPS Use of SDM QSPI Controller Programming Model x
A.2.7.1. Setting Up the QSPI Flash Controller A.2.7.2. Indirect Read Operation A.2.7.3. Indirect Write Operation
A.2.9. HPS Use of SDM QSPI Controller Design Guidelines and Examples x
A.2.9.1. Ownership and Control of Quad SPI Controller A.2.9.2. Using a Single Flash for both FPGA Configuration and HPS Mass Storage A.2.9.3. Pin Features and Connections for SDM QSPI
A.3. Security x
A.3.1. Security Differences Among Intel SoC Device Families A.3.2. ARM Security ISA A.3.3. Secure Device Manager A.3.4. Configuration Bitstream A.3.5. HPS Secure Boot A.3.6. HPS Debug A.3.7. Available Security Documentation
A.4. Operational Status of the HPS to the FPGA Logic x
A.4.1. Overview A.4.2. Software Requirements A.4.3. Signal Behavior Event Diagrams A.4.4. SDM Gated Signals
A.4.1. Overview x
A.4.1.1. SDM Gated Signals A.4.1.2. HPS Events A.4.1.3. FPGA Events
A.4.2. Software Requirements x
A.4.2.1. FPGA Boot First Mode A.4.2.2. HPS Boot First Mode
A.4.3. Signal Behavior Event Diagrams x
A.4.3.1. FPGA User Mode Entry A.4.3.2. HPS Warm Reset Event A.4.3.3. HPS Cold Reset Event A.4.3.4. Watchdog Causes HPS Warm Reset Event A.4.3.5. Watchdog Causes HPS Cold Reset Event
1. Agilex™ 5 Hard Processor System Technical Reference Manual Revision History
2. Introduction to the Hard Processor System
3. Micro Processor Unit (MPU)
4. Application Processor Subsystem
5. Peripheral Subsystem
6. System Manager
7. Clock Manager
8. Reset Manager
9. Power Management
10. Address Map
11. Bridges
12. Interfaces
13. System Interconnect and Firewalls
14. Error Checking and Correction Controller
15. CoreSight Debug and Trace
16. HPS Register Map
A. Appendix

5.1.6.3.4. Receive Descriptor

The DMA in the EMAC attempts to read a descriptor only if the tail pointer is different from the base pointer or current pointer. It is recommended to have a descriptor ring with a length that can accommodate at least two complete packets received by the MAC. Otherwise, the performance of the DMA is impacted greatly because of the unavailability of the descriptors. In such situations, the RX FIFO in MTL becomes full and starts dropping packets.

There are two receive descriptor types: normal and context descriptors. All RX descriptors are prepared by the software and given to the DMA as normal descriptors with the content. The DMA reads this descriptor and after transferring a received packet (or part of packet) to the buffers indicated by the descriptor, the RX DMA closes the descriptor with the corresponding packet status. The format of this status is given in the Receive Normal Descriptor (Write-Back Format) section.

For some packets, the normal descriptor bits are not enough to write the complete status. For such packets, the RX DMA writes the extended status to the next descriptor (without processing or using the buffers pointers embedded in that descriptor). The format and content of this descriptor write back is described in Receive Context Descriptor (Write-Back Format) section.

Receive Normal Descriptor (Read Format)

The format of the receive normal descriptor (read format) is shown in the following figure.
Figure 61. Receive Normal Descriptor (Read Format)
Note: In the receive descriptor (read format), if the buffer address field is all zeros, the EMAC does not transfer data to that buffer and skips to the next buffer or next descriptor.
The following tables describe the RDES0-3 fields for the receive normal descriptor (read format).
Table 130.  RDES0 Normal Descriptor (Read Format)
Bit Name Description
31:0 BUF1AP

Header or buffer 1 address pointer.

When the SPH bit of control register of a channel is reset, these bits indicate the physical address of buffer 1. When the SPH bit is set, these bits indicate the physical address of header buffer where the RX DMA writes the L2/L3/L4 header bytes of the received packet.

The software can program a byte-aligned address for this buffer which means that the LS bits of this field can be non-zero. However, while transferring the start of packet, the DMA performs a write operation with RDES0[3:0] (or RDES0[2:0] in case of 64-bit configuration) as zero. However, the packet data is shifted as per actual offset as given by buffer address pointer.

If the address pointer points to a buffer where the middle or last part of the packet is stored, the DMA ignores the offset address and writes to the full location as indicated by the data-width.

Table 131.  RDES1 Normal Descriptor (Read Format)
Bit Name Description
31:0 BUF1AP

In 64-bit addressing mode, this field contains the most-significant 32 bits of the header/buffer 1 address pointer. Otherwise, this field is reserved.

Table 132.  RDES2 Normal Descriptor (Read Format)
Bit Name Description
31:0 BUF2AP

Buffer 2 address pointer.

These bits indicate the physical address of buffer 2.

When the SPH bit of the DMA_CH(#i)_Control register is set, the buffer address pointer must be bus width-aligned, that is, RDES2[2:0] = 0 corresponding to 64 bus width. LSBs are ignored internally.

When the SPH bit of the DMA_CH(#i)_Control register is reset, the BUF2AP can be of any byte-aligned value. However, the RX DMA uses the LS Bits of the pointer address only while transferring the start bytes of a packet. If the BUF2AP is giving the address of a buffer in which the middle or last part of a packet is stored, the DMA ignores BUF2AP[2:0] (corresponding to 64-bit databus) and writes to the complete location.

Table 133.  RDES3 Normal Descriptor (Read Format)
Bit Name Description
31 OWN

Own bit.

When this bit is set, it indicates that the EMAC DMA owns the descriptor. When this bit is reset, it indicates that the application owns the descriptor.

30 IOC

Interrupt on completion.

When this bit is set, an interrupt is issued to the application when the DMA closes this descriptor.
29:0 BUF2AP Higher 30-bits of the buffer2 address pointer in 64-bit addressing mode. Otherwise it is reserved.

Receive Normal Descriptor (Write-Back Format)

The RX DMA frees up a descriptor by writing it back to the system memory after transferring the received packet contents to the buffers pointed by the descriptor (read format). At the same time, it also writes the status information of the current packet in the format as shown in figure below.
Figure 62. Receive Normal Descriptor (Write-Back Format)
The following tables describe the RDES0-3 fields for the receive normal descriptor (write-back format).
Table 134.  RDES0 Normal Descriptor (Write-Back Format)
Bit Name Description
For Non Tunneled Frames (TNP = 0)
31:16 IVT/ELRD Inner VLAN tag

This field contains the inner VLAN tag of the received packet. This is valid only when double VLAN tag processing and VLAN tag stripping are enabled.

This field is valid only when the L2T field of RDES0 indicates that the received packet is a double VLAN tagged packet.
Note: In case of external receive of inner VLAN lookup, this field shows the lookup index based on the RIVTBS field of the MAC_RVLAN_LKP_SIZE register programming.

External Lookup Result Data

When you enable external lookup function, this field contains the data accepted from the External Lookup Engine (xgmac_elrd_i input) when the ELD=1 and IOS=1. When status bit ELD=0, then this field corresponds to IVT.

15:0 OVT/ELRD Outer VLAN tag

This field contains the outer VLAN tag of the received packet. This is valid only when VLAN tag stripping is enabled.

This field is valid only when the L2T field of RDES0 indicates that the received packet is a VLAN or doubled VLAN tagged packet.
Note: In case of external receive of outer VLAN lookup, this field shows the lookup index based on the ROVTBS field of the MAC_RVLAN_LKP_SIZE register programming.

External lookup result data

When you enable external lookup function, this field contains the data accepted from the external lookup engine (xgmac_elrd_i input) when the ELD=1 and IOS=0. When status bit ELD=0, then this field corresponds to OVT.

For Tunneled Frames (TNP = 1)
31:8

VNID/VSID

VNID/VSID tag.

This field contains VNID for VxLAN type tunneled packet and VSID for NVGRE type tunneled packets.
7:3 RSVD Reserved
2:0 OL2L3

Outer L2 L3 type.

This field indicates the type of outer header of the received tunneled packet.
  • 001: untagged IPv6
  • 010: VLAN tagged IPv4
  • 011: VLAN tagged IPv6
  • 100: Double VLAN tagged IPv4
  • 101: Double VLAN tagged IPv6
  • 110-11: Reserved
Table 135.  RDES1 Normal Descriptor (Write-Back Format)
Bit Name Description
31:0

RSSH/FRPLI

Received side scaling hash/FRP last instruction.

When RDES3[26] bit is set and RSS hash feature is enabled, this field contains the 32-bit RSS hash calculated with some of the L3-L4 header fields of the current packet.

For a tunneled packet, this contains the non-standard RSS hash using some of the outer header and inner header fields.
Note: In case of an external RSS lookup, based on RSS lookup size, LSB of this field can be used to determine the lookup index.

When RDES3[26] bit is reset and FRP feature is enabled, this field contains the FRP last instruction number where FRP result is generated.

In case of non-receive channel list based frame duplication, when the packet is duplicated to multiple receive DMA channels, EMAC does not provide the RSS hash.

Table 136.  RDES2 Normal Descriptor (Write-Back Format)
Bit Name Description
31:29 L3L4FM

Layer 3 and Layer 4 filter number matched.

When the DHLFRS field of the MAC_Packet_Filter register is set to
  • 0x1: This field represents DA hash table index [10:8] bits, if it is valid, based on HFDAF field.
  • 0x2: This field is reserved. If bit 28 or bit 27 is set to 1, the MADRM field of the same status word indicates the layer 3 and layer 4 filter number that matched the received packet.
For all other cases, these bits indicate the number of the layer 3 and layer 4 filter that matched the received packet:
  • 000: Filter 0
  • 001: Filter 1
  • 010: Filter 2
  • 011: Filter 3
  • 100: Filter 4
  • 101: Filter 5
  • 110: Filter 6
  • 111: Filter 7

This field is valid only when bit 28 or bit 27 is set to 1. When more than one filter matches, these bits give the lowest filter number.

When more than one filter matches, these bits indicate the number of the lowest filter. For a tunneled packet, only the outer L3-L4 header fields are used for comparison.

28 L4FM

Layer 4 Filter Match.

When this bit is set, it indicates that the received packet matches one of the enabled Layer 4 Port Number fields. This status is given only when one of the following conditions is true:

  • Layer 3 fields are not enabled and all enabled layer 4 fields match
  • All enabled Layer 3 and layer 4 filter fields match

When more than one filter matches, this bit gives the layer 4 filter status of filter indicated by the following bits of the status word.

  • MADRM[5:0]: When DHLFRS field of MAC_Packet_Filter register is set to 0x02
  • Bits[31:29]: Otherwise

For a tunneled packet, only the outer L3-L4 header fields are used for filter comparison.
27 L3FM

Layer 3 filter match.

When this bit is set, it indicates that the received packet matches one of the enabled layer 3 IP address fields. This status is given only when one of the following conditions is true:
  • All enabled layer 3 fields match and all enabled layer 4 fields are bypassed
  • All enabled filter fields match
When more than one filter matches, this bit gives the layer 3 filter status of filter indicated by the following fields of the status word:
  • MADRM[5:0]: When DHLFRS field of MAC_Packet_Filter register is set to 0x02
  • Bits[31:29]: Otherwise

For a tunneled packet, only the outer L3-L4 header fields are used for filter comparison.
26:19 MADRM

MAC Address Match or Hash Value or L3L4 Filter Match.

  • When the DHLFRS field of the MAC_Packet_Filter register is set to 0x0 or 0x1:
    • When (DAIF = 0 and HFDAF = 2'b00) or (DAIF = 1 and HFDAF = 2'b01), this field contains the MAC address register number that matched the destination address of the received packet.
    • When (DAIF = x and HFDAF = 2'b1x), this field contains the hash value computed by the MAC. A packet passes the hash filter when the bit corresponding to the hash value is set in the hash filter register.

For other combinations of DAIF and HFDAF, this field is unused.

  • When the DHLFRS field of the MAC_Packet_Filter register is set to 0x2:
    • If Bit 28 or Bit 27 is set to 1, MADRM field indicates the Layer 3 and Layer 4 filter number that matched for the received packet. The number of lower bits of the MADRM (1, 2, 3, 4, or 5 bits) that are valid is based on the number of L3-L4 filters selected (2, 4, 8, 16, or 32); remaining bits are reserved.
  • When the DHLFRS field of the MAC_Packet_Filter register is set to 0x3:
    • This field is reserved.

For a tunneled packet, only the outer Ethernet header fields are used for filtering.
18:17 HFDAF

Hash Filter and Destination Address Filter Status.

This field gives combined result for both Hash DA and Perfect DA filter status.

  • When DAIF = 0
    • 2’b00: Perfect DA filter pass and don't care Hash DA filter.
      • When DHLFRS is 0x0 or 0x1. MADRM = MAC address register number that matched the DA of the received packet.
    • 2’b01: Both Perfect DA filter and Hash filter fail
      • When DHLFRS is 0x0 or 0x1, MADRM = unused.
    • 2’b1x: Perfect DA filter fail and Hash filter pass
      • When DHLFRS = 0,
        • x = 0 and MADRM = [7:0] bit of DA hash table index.
      • When DHLFRS = 1,
        • x = 11th bit, if DA hash table size>2048
        • x = 0, otherwise.
        • L3L4M = [10:8] bit and MADRM = [7:0] bit of DA hash table index
      • When DHLFRS != (0 or 1)
        • x = 0
  • When DAIF = 1
    • 2’b00: Perfect DA filter pass (no match for Perfect DA) and Hash DA filter pass (no match for Hash DA)
      • When DHLFRS is 0x0 or 0x1, MADRM = unused
    • 2’b01: Perfect DA filter fail (match for Perfect DA) and don't care Hash DA filter
      • When DHLFRS is 0x0 or 0x1, MADRM = MAC address register number that matched the DA of the received packet
    • 2’b1x: Perfect DA filter pass (no match for Perfect DA) and Hash DA filter fail (match for Hash DA).
      • When DHLFRS = 0
        • x = 1 and MADRM = [7:0] bit of DA hash table index
      • When DHLFRS = 1
        • x = 11th bit, if DA hash table size > 2048
        • x = 0, otherwise.
        • L3L4M = [10:8] bit and MADRM = [7:0] bit of DA hash table index
      • When DHLFRS != (0 or 1)
        • x = 1

For a tunneled packet, only the outer Ethernet header fields are used for filtering
17 DAF

Destination Address Filter Fail.

When this bit is set, it indicates that the packet failed the DA Filter in the MAC.

For a tunneled packet, only the outer Ethernet header fields are used for filtering.
16 SAF

SA Address Filter Fail.

When this bit is set, it indicates that the packet failed the SA Filter in the MAC.

For a tunneled packet, only the outer Ethernet header fields are used for filtering.
15 VF

VLAN Filter Status.

When this bit is set, it indicates that the VLAN Tag of received packet passed or bypassed the VLAN filter.

For a tunneled packet, only the outer Ethernet header fields are used for filtering.
14 RPNG

Response Packet Not Generated.

For ARP packets, this bit is set when the MAC is busy transmitting ARP reply to earlier ARP request (only one ARP request is processed at a time or when the Register bit ARPEN = 0).

Similarly, for PTP packets, this bit is set when the MAC is busy transmitting a PTP response to an earlier PTP packet.

This bit is reserved when the Enable IPv4 ARP Offload option or PTP Offload feature are not selected.

RPNG field is reserved for tunneled packet.
13 IOS

IVT-OVT Select.

This bit when set to 1 and when ELD=1, indicates that RDES0[31:6] field is interpreted as ELRD and contains the data read from the External Lookup Interface (xgmac_elrd_i bus).

When this bit is 0 and ELD=1, then RDES[15:0] contains the ELRD field.

This bit is reserved when “Enable External Lookup Interface” is not selected or when current packet is a tunneled packet (TNP=1).

12 ELD

ELRD valid.

This bit, when set to 1 indicates that either RDES0[31:6] field or RDES[15:0] field is interpreted as ELRD and contains the data read from the External Lookup Interface (xgmac_elrd_i bus). When this bit is 0, RDES0 reverts back to the default IVT, OVT fields. This bit is valid and set only when ELEN is set in MAC_Rx_Configuration register and the xgmac_elrd_val_i input signal from the External Lookup interface is active for this packet.

This bit is reserved when “Enable External Lookup Interface” is not selected or when current packet is a tunneled packet (TNP=1).

11 TNP

Tunnel Packet.

When this field is ‘1’, received packet is a tunneled packet. When this field is ‘0’, received packet is a non-tunneled packet. Tunneled packet recognition is enabled only when VNE of MAC_Tx_Configuration register is set.

Note: This field exists only when the EDMA field of the MAC_HW_Feature0 register is selected; Otherwise this field is Reserved.

10 RSVD Reserved
9:2 HL

L3/L4 Header Length.

This field contains the length of the header of the packet split by the MAC at L3 or L4 header boundary as identified by the MAC receiver. This field is valid only when the first descriptor bit is set (FD = 1).

The header data is written to the Buffer 1 address of corresponding descriptor. If header length is zero, it implies that the MAC did not identify and split the header and both Buffer 1 and Buffer 2 are used for storing the packet.

For VxLAN tunneled packets, header length = (header length of outer packet + eight bytes of VxLAN header + header length of inner packet).

For NVGRE tunneled packets, header length = (outer packet’s header length +inner packet’s header length).

This field is valid when the Enable Split Header Structure option is selected.
1 AVTDP

AV Tagged Data Packet.

When L34T = 0000, this bit is set to 1 when AV Tagged Data packet is received.

When L34T is non-zero, this bit is HL[1] for packet split by the MAC at L3 or L4 header.
0 AVTCP

AV Tagged Control Packet.

When L34T = 0000, this bit is set to 1 when AV Tagged Control packet is received.

When L34T is non-zero, this bit is HL[0] for packet split by the MAC at L3 or L4 header.

In the write-back format, all the status fields (except bits[31:28]) are valid only for the last descriptor (when RDES3[28] is set).

Table 137.  RDES3 Normal Descriptor (Write-Back Format)
Bit Name Description
31 OWN

Own Bit.

DMA clears this bit (to 0) to indicate that it has transferred the data to the buffers and the descriptor is now owned by the software. The DMA clears this bit when either of the following conditions is true:

  • The DMA completes the packet transfer
  • The buffers associated with the descriptor are full
30 CTXT

Receive Context Descriptor.

When this bit is set, it indicates that the current descriptor is a context type descriptor. The DMA writes 1'b0 to this bit for normal receive descriptor.

29 FD

First Descriptor.

1: Indicates that this descriptor contains the first buffer of the packet.

If the size of the first buffer is 0, the second buffer contains the beginning of the packet. If the size of the second buffer is also 0, the next descriptor contains the beginning of the packet.

CTXT, FD, and LD bits together indicate Descriptor Definition Error. During write-back, all three bits are set to 1 {CTXT, FD, LD} = 3’b111, to indicate Descriptor Definition Error in the Rx Descriptor. Descriptor Definition Error for Rx Descriptor is indicated when both Buffer-1 and Buffer-2 are all 1s. On encountering this error, the Receive DMA terminates the ongoing DMA transfer, flushes the ongoing packet in the Receive Queue and enters stop state.

The DEE and RPS fields of the corresponding DMA_CH(#i)_Status register is set to 1.

Recovery Mechanism: Perform a software reset by programming the SWR field of the DMA_Mode register to 1.
28 LD

Last Descriptor.

When this bit is 1,

  • Indicates that the buffers to which this descriptor is pointing. Contains end of packet.
  • Rest of the status fields in RDES0, RDES1, and RDES3 provide information about the packet.
27 CDA

Context Descriptor Available.

When this bit is set, the next descriptor following this descriptor is a Context Descriptor.
26 RSV

RSS Valid.

When this bit is set, it indicates that valid RSS Hash is available in RDES1[31:0]. This bit is valid only when the RSS function is enabled MAC_RSS_Control register. In case of non-receive channel list based frame duplication, when packet is duplicated to multiple Receive DMA channels, this field is 0.

25 ISP

In Sequence Packet.

When this bit is reset, it indicates that this packet is not in sequence (TCP sequence number) with respect to the previous packet transferred by this DMA, or the RSS Hash value is different for this packet with respect to the RSS Hash calculated and given for the previous packet.

When this bit is set, it indicates that this TCP packet is in sequence with respect to the previous packet transferred by this DMA and the RSS hash values also match. The application can do a TCP coalescing of this packet with the previous packet transferred by this DMA.

This bit is valid only when the OoS function is enabled in MAC_RSS_Control register. This bit is not valid if it is a tunneled packet.(TNP=1)

24

ETM/

NCP

Ether Type Match / No Coalescing Packet.

When L34T=000, this bit is set to 1 (ETM Status) when the “Type” field of the received packet matches the value programmed in the MAC_Rx_Eth_Type_Match register.

When L34T has any value other than 000 and this bit is set to 1 (NCP Status), it indicates that the DMA has received a packet that must not be kept holding for TCP packet coalescing. It must be forwarded to the TCP/IP stack immediately even though it may be in sequence with respect to the previous packet.

NCP Status is valid only when the OoS function is enabled in the MAC_RSS_Control register.

For a tunneled packet, ETM refers to the Type Match of the Inner Ethernet Header.

NCP is not supported for a tunneled packet.
23:20 L34T

Layer3 / Layer4 packet Type.

These bits indicate the type of payload encapsulated in the IP datagram and processed by the Receive Checksum Offload Engine (RxCOE).

For a tunneled packet, the Layer3/Layer4 packet type refers to the L3/L4 type of the inner packet.

This field is valid only when the LD field is set.

  • 0000: Not an IP packet
  • 0001: IPv4 packet with TCP Payload as Layer4
  • 0010: IPv4 packet with UDP Payload as Layer4
  • 0011: IPv4 packet with ICMP Payload as Layer4
  • 0100: IPv4 packet with IGMP Payload is Layer4
  • 0101 to 0110: Reserved
  • 0111: IPv4 with unknown (unsupported) payload
  • 1000: Reserved
  • 1001: IPv6 packet with TCP Payload as Layer4
  • 1010: IPv6 packet with UDP Payload as Layer4
  • 1011: IPv6 packet with ICMP Payload as Layer4
  • 1100 to 1110: Reserved
  • 1111: IPv6 with unknown (unsupported) payload
19:16 ET/LT

Error Type or L2 Type.

When the 15th bit of this descriptor (ES) is set to 1, this field indicates the Error Type.

When the 15th bit of this descriptor (ES) is set to 0, this field indicates the L2 Packet Type.

Following is the encoding:

When ES = 1 (Error Type Encoding)

  • 0000: Reserved
  • 0001: Watchdog Timeout Error
    • It indicates that the Receive Watchdog Timer has expired while receiving the current packet.
    • The current packet is truncated after watchdog timeout.
  • 0010: Invalid Code Error or GMII Error
    • In GMII mode, it indicates that the RX_ER and RX_DV signals were asserted for the frame, indicating a receive error signaled to the GMII.
  • 0011: CRC Error
    • It indicates that a Cyclic Redundancy Check (CRC) Error occurred on the received packet.
  • 0100: Giant Packet Error
    • It indicates that the packet length exceeds the specified maximum Ethernet size of 1518,1522, or 2000 bytes (9018 or 9022 bytes if jumbo packet enable is set).
    • Note: Giant packet indicates only the packet length. It does not cause any packet truncation.
  • 0101: IP Header Error
    • It indicates that the 16-bit IPv4 Header checksum calculated by the EMAC controller does not match the received Checksum bytes or that the IP datagram version is not consistent with the Ethernet Type value.
    • This error is possible only when you select the Enable Receive TCP/IP Checksum Check feature
  • 0110: Payload (L4) Checksum Error
    • It indicates that the 16-bit IP payload checksum (that is, the TCP, UDP, or ICMP checksum) calculated by the EMAC controller does not match the received TCP, UDP, or ICMP checksum field.
  • 0111: Overflow Error
    • It indicates that the received packet is damaged because of buffer overflow in Rx FIFO.
    • Note: This bit is set only when the DMA transfers a partial packet to the application. This happens only when the Rx FIFO is operating in the threshold mode. In the store-and-forward mode, all partial packets are dropped completely in Rx FIFO.
  • 1000: Bus Error
    • It indicates that Bus Error response is received while fetching this descriptor or when packet is being transferred to its buffers.
  • 1001: Length Error
    • It indicates that the Length value of the current frame is inconsistent with the total number of bytes received in the current frame. This is applicable when Frame Length value is less than 1500. This error is reported when the following type of frames are received:
    • Frames in which the value of the Length field is less than 46 bytes and the length of the received frame is less than the following:
    • Length field + 18 bytes
    • Frames in which the value of the Length field is equal to or greater than 46 bytes and the length of the received frame is not equal to the following:
    • Length field + 18 bytes
  • 1010: Good runt packet. Packet less than 64 bytes but with good CRC.
  • 1011: Reserved
  • 1100: Dribble Error
    • Indicates that, in the 10/100Mbps speed mode, the packet has ended without a byte boundary.
  • 1101 -1110: Reserved for non-tunneled packets
  • 1111: Safety Error
    • In the case of tunneled packet (TNP = 1), the error status is extended to differentiate between the errors in outer Header or Inner Header. In the status types, the following values are applicable for the Outer Header fields:
  • 0101: Outer IP Header Error
  • 0110: Outer Header's Payload (L4) Checksum Error
    • Additionally, the following Error Status types are applicable
  • 1001: Inner Packet IP Header Error
  • 1010: Inner Packet Payload (L4) Checksum Error
  • 1101-1110: Reserved for tunneled packets
    • When ES = 0 (L2 Packet Type Encoding)
  • 0000: The packet is a length packet.
  • 0001: The packet is a MAC Control packet.
  • 0010: DCB Control Packet.(Note: Inner Header of a tunneled packet is not parsed for DCB Control type)
  • 0011: The packet is of ARP Request Packet Type.
  • 0100: The packet is of OAM packet type.(Note: Inner header of a tunneled packet is not parsed for OAM Control type)
  • 0101: The untagged packet has a Type field which matched the value in the MAC_Rx-_Eth_Type_Match register
  • 0110 – Untagged AV Control packet
  • 0111: The packet is an other Type Packet.
  • 1000: The packet is type packet with Single SVLAN tag.
  • 1001: The packet is type packet with Single CVLAN tag.
  • 1010: The packet is type packet with Double VLAN tag with outer VLAN is CVLAN and inner is also CVLAN.
  • 1011: The packet is type packet with Double VLAN tag with outer VLAN is SVLAN and inner is SVLAN.
  • 1100: The packet is type packet with Double VLAN tag with outer VLAN is SVLAN and inner is CVLAN
  • 1101: The packet is type packet with Double VLAN tag with outer VLAN is CVLAN and inner is SVLAN.
  • 1110 - 1111: Reserved

For a tunneled packet, the L2 packet type encoding refers to the L2 type of the Inner packet.
15 ES

Error Summary.

This bit indicates that the received packet has an error. The type of error is indicated by bits

[19:16].

This field is valid only when the LD bit of RDES3 is set.

When this field is 1, indicates safety error.
14 RSVD Reserved
13:0 PL

Packet Length.

These bits indicate the byte length of the received packet that was transferred to system

memory. This does not include the VLAN/Pad/CRC bytes if VLAN/Pad/CRC stripping is

enabled. This field is valid when the LD (bit[28]) field of RDES3 is set and there is no

overflow error indication in ET/LT(bits[19:16]).

Receive Context Descriptor (Write-Back Format)

The receive context descriptor provides information about the extended status of the last received packet. Bit 30 of RDES3 indicates the context type descriptor.
Figure 63. Receive Context Descriptor
Table 138.  RDES0 Context Descriptor
Bit Name Description
31:0 RTSL

Receive packet timestamp low.

The DMA updates this field with the least significant 32 bits of the timestamp captured for the corresponding receive packet. When this field and the RTSH field of RDES1 show a value of all ones, the timestamp must be considered as corrupt.

Table 139.  RDES1 Context Descriptor
Bit Name Description
31:0 RTSH

Receive packet timestamp high.

The DMA updates this field with the most significant 32 bits of the timestamp captured for the corresponding receive packet. When this field and the RTSH field of RDES1 show a value of all ones, the timestamp must be considered as corrupt.

Table 140.  RDES2 Context Descriptor
Bit Name Description
31:0 RSVD

Reserved
Table 141.  RDES3 Context Descriptor
Bit Name Description
31 OWN

Own bit.

DMA clears this bit to 0, to indicate that the status is written in the descriptor and is now owned by the software.
30 CTXT

Receive context descriptor.

When this bit is set, it indicates that the current descriptor is a context descriptor. The DMA writes 1'b1 to this bit for context descriptor.

29:20 RSVD Reserved
19:16 ET/ST

Error type/Status type.

  • When ES = 1, this field indicates the error type
  • When ES = 0, this field indicates status type

Status type

  • 0000 - 1111: Reserved

Error type

  • 0000 - 1110: Reserved
  • 1111: Safety Error
15 ES

Error summary.

  • 1: Indicates that ET/ST (bits 19:16) is error type
  • 0: Indicates that ET/ST (bits 19:16) is status type
14:7 RSVD Reserved
6 TSD

Timestamp dropped.

When set, it indicates that a timestamp was captured for this packet but was dropped due to the lack of space in Rx FIFO. The host must consider the RTSL and RTSH as valid only when TSD=0 and TSA=1

5 PRPNG

PTP response packet not generated.

When set, it indicates that a PTP Response packet was not generated by the MAC for this received PTP Packet. This bit is valid only when the PTP Offload Feature is enabled in your configuration.

4 TSA

Timestamp available.

When set, this bit indicates that the timestamp value is available in RDES0 and RDES1 of the context descriptor.
3:0 PMT

PTP message type:

These bits are encoded to give the type of the PTP message received:

  • 0000: No PTP message received
  • 0001: SYNC (all clock types)
  • 0010: Follow-up (all clock types)
  • 0011: Delay_Req (all clock types)
  • 0100: Delay_Resp (all clock types)
  • 0101: Pdelay_Req (in peer-to-peer transparent clock)
  • 0110: Pdelay_Resp (in peer-to-peer transparent clock)
  • 0111: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)
  • 1000: Announce
  • 1001: Management
  • 1010: Signaling
  • 1011-1110: Reserved
  • 1111: PTP packet with Reserved message type
Level Two Title