Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs
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5.15.5.3.3. FPGA Access MUX Registers
The FPGA access MUX registers (sometimes called “use FPGA” registers) select whether each HPS peripheral uses HPS I/O pins or is routed to the FPGA fabric.
You can route some of the peripherals to the FPGA. The following FPGA access registers are available:
- pinmux_emac0_usefpga
- pinmux_emac1_usefpga
- pinmux_emac2_usefpga
- pinmux_i2c0_usefpga
- pinmux_i2c1_usefpga
- pinmux_i2c_emac0_usefpga
- pinmux_i2c_emac1_usefpga
- pinmux_i2c_emac2_usefpga
- pinmux_i3c0_usefpga
- pinmux_i3c1_usefpga
- pinmux_spim0_usefpga
- pinmux_spim1_usefpga
- pinmux_spis0_usefpga
- pinmux_spis1_usefpga
- pinmux_uart0_usefpga
- pinmux_uart1_usefpga
- pinmux_mdio0_usefpga
- pinmux_mdio1_usefpga
- pinmux_mdio2_usefpga
At cold reset, the FPGA access MUX registers default to HPS I/O pins. A warm reset event does not affect these registers.