5.5.6.4.1. DLL Locking

Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

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Date 4/01/2024

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5.5.6.4.1. DLL Locking

The DLL locking process consists of determining the number of delay elements in one clk_phy clock cycle or half cycle, depending on the DLL lock mode (full clock or half clock mode). Once this is determined, the dll_lock bit in the phy_dll_obs_reg_0 register is set. Also, the number of delay elements is reported in the dll_lock_value filed in the same register. The DLL uses this value to generate the DLL delayed output signals using the programmable deskew values in the configuration registers (that is, the delay applied to the output signal is proportional to the dll_lock_value).

DLL locking is controlled through the register interface. When the DLL is reset by asserting the PHY reset signal, the primary DLL performs a locking procedure starting with the programmed value in the param_dll_start_point field in the phy_dll_master_ctrl_reg register and the current frequency of operation. The param_dll_start_point field should be programmed with a value that does not exceed 7/8ths of a clock period given the worst-case element delay. For example, if the frequency is 200 MHz (5ns cycle time) with a worst-case element 80ps delay, this field should be set to = 5* (7/8) / .080 = 54 elements. With this setting, the primary DLL is guaranteed to correctly lock for all frequencies below 200 MHz and in any corner condition. Adjust this parameter to reduce the DLL lock time.

If the delay provided by the delay line is enough to cover a full clock cycle, the primary DLL is in full clock mode. In this case, the dll_lock_value in the phy_dll_obs_reg_0 register reports the number of delay elements in one full clock cycle. This number is used by the secondary delay line fractional settings to determine the number of elements of delay to add to the secondary delay lines. For example, if the dll_lock_value = 50 and the secondary delay line percentage = 25% (64/256), then the secondary delay line delay value = 50 * .25 = 12.5 elements (rounded to integer).

If the frequency of operation is such that the delay line is not long enough to accommodate a full cycle of delay, the primary DLL automatically detects this situation and switches to half clock mode. In this mode, the primary DLL attempts to lock when the delay in the delay line reaches a half-clock cycle. If lock is achieved in half clock mode, the secondary delay lines are automatically adjusted multiplying the dll_lock_value by 2 to represent the full cycle. There is no need to change the secondary delay settings based on the lock mode of the primary DLL. For example, if the dll_lock_value = 50 and the secondary delay line percentage = 25% (64/256), then the secondary delay line delay value = (50x2) * .25 = 25 elements.

If the frequency of operation is such that the delay line is not long enough to capture a half-clock cycle of delay, the primary DLL indicates lock and sets the number of delays to the maximum length of the delay line. This is called saturation mode. There is no need to change the secondary delay settings in this mode. The secondary delay settings are fixed at the fractional delay based on the maximum delay of the delay line multiplied by 2. For example, if the dll_lock_value = MAX (255) and the secondary delay line percentage = 25% (64/256) then the secondary delay line delay value = (255x2) * .25 = 128 elements.

Note: In half clock mode or saturation mode, if the secondary delay line is programmed to more than 50% delay, the input clock to the secondary delay line is inverted (that is, half cycle delayed) and the percentage delay used by the secondary delay line is reduced by 50%. For example, if the dll_lock_value = 50, and the secondary delay line percentage = 85% (217/256), then the secondary delay line delay value = (50 x 2) * (.85 - .50) = 43 elements + one half-clock. This feature does not apply to the read DQS delay line since the delay needed for the read DQS is always between 0 and 50%.

During the DLL locking process, the phase detector block provides the mechanism to determine that the delay applied to the input signal corresponds to 1 cycle (or half cycle depending on the operation mode). This is done by detecting edge transitions between the input signal and the delayed signal (1->0 or 1->0). The phase detector also includes a delay line and in general the lock condition is achieved when the current number of delay elements in the primary delay line is such that the edge leaving the delay line is within the delta delay generated by the phase detect delay line. The number of delay elements phase detector delay line can be configured using the param_phase_detect_sel field in the phy_dll_master_ctrl_reg register supporting up to 8 delay elements. A block diagram of the primary delay line connected to the phase detector is shown next.

Figure 156. Primary DLL Delay Path

Ideally, the phase detect delay should be just wide enough so that when in full clock mode, the first synchronizer in the phase detect captures a 1 and the second phase detect synchronizer captures a 0. The phase detect should not be so wide as to create a situation where there are multiple delay values of the secondary delay line that have the first synchronizer read a 0 and the second synchronizer read a 1. This would create more errors in the secondary delay lines. Conversely, if the phase detect is too narrow, the first and second phase detect synchronizer always return the same value. This would create an oscillation between adding or subtracting multiple increments or decrements. This would also increase the error in the secondary delay line settings since there would not be an accurate value of the number of delay elements in one cycle.

The delay configuration in the secondary delay lines for the signals generated by the DLL is done using the phy_dll_slave_ctrl_reg register. Each of the 8-bit fields corresponds to one of the DLL output signals shown in the DLL block diagram.

As an alternative to go through the DLL locking process to achieve the initial lock, we can also set the param_dll_bypass_mode bit in the phy_dll_master_ctrl_reg. When doing this, the dll_lock bit in the phy_dll_obs_reg_0 is forced to 1. In this case, only 1 delay element is applied in the primary delay line and the values set in the secondary delay lines become absolute instead of fractional delays.

Once DLL gets locked in any of the mechanisms described above, the dfi_init_complete signal is asserted. The primary DLL remains locked until this signal is reset (by clearing PHY reset or DLL reset).

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Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

5.5.6.4.1. DLL Locking