AXI Streaming Intel® FPGA IP for PCI Express* User Guide
Visible to Intel only — GUID: jow1700067220953
Ixiasoft
Visible to Intel only — GUID: jow1700067220953
Ixiasoft
6. Interfaces and Signals
This section focuses mainly on the signal interfaces that the AXI Streaming Intel® FPGA IP for PCI Express* uses to communicate with the Application Layer in the FPGA fabric core. It also briefly covers the Serial Data Interface, which allows the IP to communicate with the link partner across the PCIe* link.
Section Content
Overview
Clocks and Resets
Application Packet Interface
Configuration Extension Bus Interface
Configuration Intercept Interface
Function Level Reset Interface
Control Shadow Interface (st_ctrlshadow)
Completion Timeout Interface (st_cplto)
Miscellaneous Signals
Control and Status Register Responder Interface (lite_csr)
Error Interface (st_err)
VF Error Flag Interface (vf_err/sent_vfnonfatalmsg)
VIRTIO PCI Configuration Access Interface
Serial Data Signals