AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

6.13.1. VIRTIO PCI* Config Access Request Interface (st_virtio_pcicfgreq)

Table 67.  VIRTIO PCI* Configuration Access Request Interface
Signal Name Direction Clock Domain Description
ss_app_virtio_pcicfgreq_tvalid Output axi_lite_clk When asserted, indicates a VIRTIO PCI* Configuration Access Request received from HOST. The signal is valid for one clock cycle.
ss_app_virtio_pcicfgreq_tdata[95:0] Output axi_lite_clk

[0] - When set, the request is a write request. Else, the request is a read request.

[1] - Indicates request is for Virtual Function implemented in slot's physical function

[12:2] - Indicates child VF Number of parent PF indicated by PF Number

[15:13] - The PF Number of the Request

[20:16] - The Slot Number of the Request

[28:21] - The BAR value to be used for the Request

[60:29] - The BAR Offset value to be used for the Request

[63:61] - The Length value to be used for the Request

[95:64] - The Data value to be used for the Write Request. N/A for Read Request.