AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

6.3.5. Data and Header Packing Schemes

The AXI Streaming Intel® FPGA IP for PCI Express* provides separate interfaces for data and header. The IP supports the following packing schemes:

  • HIP Native mode packing
  • Simple packing
  • Compact packing